A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications

Young, K.K.; Wu, Shien‐Yang; Wu, C.C.; Wang, C.H.; Lin, Chih−hung; Cheng, J.Y.; Chiang, Meng-Hsueh; Chen, S.H.; Lo, Tien-Yu; Chen, Y.S.; Chen, J.H.; Chen, L.J.; Hou, S. Y.; Law, Jeremy J. M.; Chang, Tzu-Heng; Hou, Chin-Shan; Shih, J.R.; Jeng, S. J.; Hsieh, Han-Chang; Ku, Yao-Ching; Yen, Ta‐Jen; Tao, Hun-Jan; Chao, Luke; Shue, S.L.; Jang, Shin Yi; Ong, T.C.; Yu, C.H.; Liang, Ming-Chung; Diaz, C.H.; Sun, J.Y.-C.

doi:10.1109/iedm.2000.904382

Cited by 34 publications

(15 citation statements)

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“…The dependence on the spacing to the adjacent ground line ( in micrometers) is so small that it can almost be ignored. At frequencies between 7-20 GHz, the frequency dependence is even weaker and (1) reduces to (2) It is important to note that this formula is a fit to our specific test chip and process. As the technology scales to more layers of metal, the inductance dependence on spacing is expected to reduce.…”

Section: A On-chip Inductancementioning

confidence: 99%

“…The conventional aluminum-silicon dioxide interconnect scheme has been considered a serious limitation to further scaling [1]. This has prompted an industry-wide shift from aluminum to copper interconnects to reduce the resistance, and a relentless search for a reliable low-permittivity dielectric material to reduce the capacitance [2], [3]. However, for wide lines and buses, resistance B. Kleveland is with Matrix Semiconductor, Santa Clara, CA 95054 USA (e-mail: bendik@matrixsemi.com).…”

Section: Introductionmentioning

confidence: 99%

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High-frequency characterization of on-chip digital interconnects

Kleveland

Madden³

et al. 2002

IEEE J. Solid-State Circuits

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Section: A On-chip Inductancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High-frequency characterization of on-chip digital interconnects

Kleveland

Madden³

et al. 2002

IEEE J. Solid-State Circuits

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“…In general, the drain-to-bulk breakdown voltage is at least twice the normal operating voltage in the standard CMOS process [9], [10]. Hence, the drain-to-bulk breakdown issue would be ignored in the proposed 2xVDD-tolerant I/O buffer.…”

Section: B Circuit Scheme and Operation Modesmentioning

confidence: 99%

Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices

Ker

Lin

2009

2009 IEEE Custom Integrated Circuits Conference

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A new 2xVDD-tolerant I/O buffer realized with only 1xVDD devices has been proposed and verified in a 0.18-µm CMOS process. With the dynamic source output technique and the new gate-controlled circuit, the new proposed I/O buffer can transmit and receive the signals with the voltage swing twice as high as the normal power supply voltage (VDD) without suffering gate-oxide reliability problem. The proposed 2xVDD-tolerant I/O circuit solution can be implemented in different nanoscale CMOS processes to meet the mixed-voltage interface applications in microelectronic systems.

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“…HYBRID SOURCE/DRAIN MODELING A hybrid (Arsenic + Phosphorus) Source/Drain is still a competent candidate for advanced CMOS technologies [4] because it is very useful for reducing junction capacitance and for alleviating polysilicon depletion under tight thermal budget processes. The profile near the arsenic junction becomes graded because of the rapid diffusion of phosphorus inside the highly doped arsenic region.…”

Section: Imentioning

confidence: 99%

Junction engineering and modeling for advanced CMOS technologies

Wang

Huang

Diaz

2003

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.

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This paper discusses an integrated modeling approach for diffusion profiles in advanced CMOS technologies. First, for USJ (Ultra-Shallow Junction) arsenic modeling, in addition to a fully-coupled model with implant damage, amorphous layer formation which depends on the Frenkel pair concentration and evolution of {311} defects and dislocation loops based on EOR (End of Range) defects are also used. Secondly, in order to improve polysilicon activation, a hybrid (arsenic + phosphorus) Source/Drain is used for NMOS. We also address the calibration of the hybrid Source/Drain for with various anneal temperatures. It is shown that modeling of the hybrid Source/Drain profile can be achieved by optimization of the dopant's Fermi level dependent diffusivity and the initial value of the point defect concentration in the equilibrium state. Finally, uphill diffusion at low anneal temperature is observed for BF2 USJ and is enhanced with Ge pre-implants. It is caused by a steep interstitial gradient created by preamorphisation and EOR damage, ultra-shallow boron profile, and boron long-hop diffusion [1] [2]. A BIC (Boron-Interstitial Cluster) model is employed to model boron diffusion after a spike RTA at both extension and S/D regions.

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A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications

Cited by 34 publications

References 0 publications

High-frequency characterization of on-chip digital interconnects

High-frequency characterization of on-chip digital interconnects

Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices

Junction engineering and modeling for advanced CMOS technologies

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