A 0.18¿¿m CMOS Receiver with Decision-feedback Equalization for Backplane Applications

Li, Miao; Kwaśniewski, T.; Wang, Shoujun

doi:10.1109/apccas.2006.342266

Cited by 2 publications

(3 citation statements)

References 6 publications

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“…A decision feedback equalizer (DFE) can cancel the post-cursor ISI without any high-frequency noise enhancement [3]. In a DFE, the results of the decision of previously received symbols have to be fed back to the current symbol before it is decided whether the current symbol is "1" or "0" [4]. Therefore the delay of the feedback loop has to be smaller than 1-UI to compensate the ISI at the center of the data eye, that is, the data sample [5].…”

Section: Introductionmentioning

confidence: 99%

Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples

Bae

Yoo

2014

IEICE Electron. Express

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A 3-Gbps decision feedback equalizer (DFE) compensating for data and edge inter-symbol interference (ISI) is presented. A speculative architecture is employed to relieve the timing burden on the feedback signal for the DFE wherein the ISI of edge sample is compensated by speculating the DFE based on two-UI earlier data sample. Thereby, the timing margins of the DFE for data and edge ISI compensation are ensured to be larger than 1.0-UI. The proposed DFE has been implemented in a 0.13-µm CMOS technology together with a clock and data recovery (CDR) circuit. The DFE and CDR circuits occupy 0.28-mm 2 active area and the DFE consumes 18-mW from a 1.2-V supply. The RMS jitter of the recovered clock is improved from 15.6-ps to 11.9-ps by the proposed edge ISI compensating DFE.

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Section: Introductionmentioning

confidence: 99%

Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples

Bae

Yoo

2014

IEICE Electron. Express

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“…The equalizer based on the digital circuit is discussed in this thesis. The equalizer can be linear [10,17], non-linear [18][19][20] or both [16,21]. The linear equalizer can be implemented on the transmitter side [10,22] or on the receiver side [21,23]…”

Section: Figure 24: Group Delay Of Channel B20mentioning

confidence: 99%

“…19 shows the post layout simulation eye diagram for different extraction strategies. The power supply is IV.…”

mentioning

confidence: 99%

A reduced power, 6-tap programmable pre-emphasis circuit

Cheng¹

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The author has granted a nonexclusive license allowing Library and Archives Canada to reproduce, publish, archive, preserve, conserve, communicate to the public by telecommunication or on the Internet, loan, distribute and sell theses worldwide, for commercial or noncommercial purposes, in microform, paper, electronic and/or any other formats. L'auteur a accorde une licence non exclusive permettant a la Bibliothfeque et Archives Canada de reproduire, publier, archiver, sauvegarder, conserver, transmettre au public par telecommunication ou par ('Internet, preter, distribuer et vendre des theses partout dans le monde, a des fins commerciales ou autres, sur support microforme, papier, electronique et/ou autres formats.

show abstract

A 0.18¿¿m CMOS Receiver with Decision-feedback Equalization for Backplane Applications

Cited by 2 publications

References 6 publications

Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples

Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples

A reduced power, 6-tap programmable pre-emphasis circuit

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