This paper describes a delta-sigma ( A-Z ) modulation and fractional-S frequency division technique to perform indirect digital frequency synthesis based on the use of a phaselocked loop (PLL). The use of 1 -Y modulation concepts results in a beneficial noise shaping of the phase noise (jitter) introduced by fractional-S division. The technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractional--Y PLL techniques. Phase Detector Loop Filter vco Spurious Frequencies Precision Analog Components Required Minimum Complexity of Digital Hardware Introduces Broad Band

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CMOS inductorless voltage controlled oscillator (VCO) design is discussed with the emphasis on low-noise, low-power, gigahertz-range circuits suitable for portable wireless equipment. The paper considers three VCO structures-one simple ring oscillator and two differential circuits. The design methodology followed optimization for high-speed and low-power consumption. The proposed linearized MOSFET model allows the accurate prediction of the operating frequency while the phase noise evaluation technique makes it possible to determine, through simulation, the relative phase-noise performance of different oscillator architectures. The measurement results of three VCO's implemented in 1.2-m CMOS technology confirm with the simulation predictions. The prototype VCO's exhibits 926-MHz operation with 083 dBc/Hz phase noise (@ 100 kHz carrier offset) and 5 mW (5 V) power consumption. Index Terms-CMOS oscillator, ECO, emitter coupled oscillator, linearized MOSFET model, multivibrator, phase locked loop, phase noise simulation, PLL frequency synthesizer, relaxation oscillator, ring oscillator, VCO, voltage controlled oscillator.

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