CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications

Thamsirianunt, M.; Kwaśniewski, T.

doi:10.1109/4.634659

Cited by 57 publications

(24 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Typical oscillators on a digital IC use some form of Voltage Controlled Oscillator (VCO) [7], [8], [9], [10], [11], and implement a PLL with the VCO in a closed-loop configuration. A phase frequency detector (PFD) determines the phase error, and accordingly either speeds up or slows down the oscillation frequency of the VCO.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A PLL design based on a standing wave resonant oscillator

Karkala

Bollapalli

Garg

et al. 2009

2009 IEEE International Conference on Computer Design

View full text Add to dashboard Cite

Abstract-In this paper, we present a new continuously variable high frequency standing wave oscillator, and demonstrate its use in generating the phase locked clock signal of a digital IC. The ring based standing wave resonant oscillator is implemented with a plurality of wires connected in a mobius configuration, with a cross coupled inverter pair connected across the wires. The oscillation frequency can be modulated by two means. Coarse modification is achieved by altering the number of wires in the ring that participate in the oscillation, by driving a digital word to a set of passgates which are connected to each wire in the ring. Fine tuning of the oscillation frequency is achieved by varying the body bias voltage of both the PMOS transistors in the cross coupled inverter pair which sustains the oscillations in the resonant ring. We have validated our PLL design in a 90nm process technology. 3D parasitic RLCs for our oscillator simulations were extracted, with skin effect accounted for. Our PLL has been implemented to provide a frequency locking range from ∼6 GHz to ∼9 GHz, with a center frequency of 7.5 GHz. The oscillator alone consumes about 25 mW of power, and the complete PLL consumes a power of 28.5 mW. The observed jitter of the PLL is 2.56%.

show abstract

Section: Introductionmentioning

confidence: 99%

“…• Digitally Controlled Oscillators (DCOs) [9], [10], [11], in which a large number of inverters are implemented such that inverter i drives the input to inverter i + 1. By closing the loop at the k th inverter (where k is odd), the oscillator can be made to oscillate at variable frequencies.…”

Section: Introductionmentioning

confidence: 99%

A PLL design based on a standing wave resonant oscillator

Karkala

Bollapalli

Garg

et al. 2009

2009 IEEE International Conference on Computer Design

View full text Add to dashboard Cite

show abstract

“…The use of multiple inverter integrators provides a higher Q than for a single stage relaxation oscillator [9]. It was demonstrated in reference [9] that CMOS VCOs designed as ring oscillators can achieve higher frequencies and better phase noise performance (comparable to monolithic LC oscillators) than other CMOS VCO designs and lower power consumption than VCOs designed using compatible technologies. …”

Section: Relaxation Oscillatorsmentioning

confidence: 99%

“…LC oscillators have a high Q factor by the nature of its design: a good quality inductor and a minimal number of active components. LC oscillators have a Q factor that is typically four times the Q factor of a relaxation oscillator [9]. High frequency applications require oscillators with high Q factors.…”

Section: Q Factormentioning

confidence: 99%

Voltage Controlled Oscillators

The International Series in Engineering and Computer Science

View full text Add to dashboard Cite

IntroductionA key circuit used in modern communication systems is the voltage controlled oscillator (VCO). The VCO's output is an AC waveform whose frequency is dependent upon the input voltage. In today's wireless communication systems, a greater maximum frequency range is required by VCOs. With respect to the digital phones that use these circuits, low power consumption, small size and low fabrication costs are important design factors.This report is an introduction to voltage controlled oscillators. Two styles of VCO (the LC oscillator and the RC relaxation oscillator) are described as well as the factors that influence their design and selection, the recent advances in the design of these circuits, and the next probable advance of these circuits in the state of the art.Background

show abstract

“…A Dual-Modulus Divider (DMD) is used to frequency scale the feedback VCO frequency. The dc frequency control value is maintained by the output of a phase/frequency detector, which serves as an "error amplifier" [1]. PFD provides the phase difference between the input reference signal and the feedback signal from the VCO.…”

Section: Introductionmentioning

confidence: 99%

A completely integrated, low noise, low power CMOS frequency synthesizer for GSM communications

Waheed¹,

Seddighrad²,

Salam³

The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002.

View full text Add to dashboard Cite

A low power 22-mW 900MHz Frequency Synthesizer (FS), with an on-chip LC-tuned voltage controlled oscillator (VCO) for GSM applications is presented. The synthesizer possesses several novel features that include a completely integrated structure, a low phase noise on-chip LC VCO, a low-power Dual-Modulus Divider (DMD) in CML topology, a compensated charge pump with balanced switching, an on-chip third order loop filter and a proposed relatively easy to implement fractional accumulator based frequency synthesis technique. The complete synthesizer achieves in-band phase noise characteristics better than -110 dBc/Hz at 100kHz offset. The channel switching time is less than 500µs for a 25MHz frequency hop. The synthesizer is able to accommodate all 195 transmit and receive channels in the R-GSM band. The proposed architecture has been realized using the 0.5 µm AMI C5N technology. The complete integrated synthesizer occupies less than 1500 × 700 µm 2 of die real estate.

show abstract

CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications

Cited by 57 publications

References 20 publications

A PLL design based on a standing wave resonant oscillator

A PLL design based on a standing wave resonant oscillator

Voltage Controlled Oscillators

A completely integrated, low noise, low power CMOS frequency synthesizer for GSM communications

Contact Info

Product

Resources

About