A 0.18 μm fully depleted CMOS on 30 nm thick SOI for sub-1.0 V operation

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation (CLM) and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

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“…Fig. 6 shows the threshold voltage roll-off of the FD SOI NMOS device with a front gate oxide of 4.5 nm for various thin-film thicknesses [35].…”

Section: Structure Dependencementioning

confidence: 99%

Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review

Chaudhry

Kumar

2004

IEEE Trans. Device Mater. Relib.

397

134

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“…A significant short channel phenomenon known as threshold voltage roll off occurs when the threshold voltage drops as the gate length decreases. Short-channel MOSFETs switch on at a smaller gate voltage than long-channel MOSFETs as a consequence [2][3][4]. By lowering the channel length, the area of the gate oxide and the gate oxide capacitance have dropped.…”

Section: Introductionmentioning

confidence: 99%

Mathematical Modeling and Performance Evaluation of 3D Ferroelectric Negative Capacitance FinFET

Alam

Uddin

Alam

et al. 2022

Modelling and Simulation in Engineering

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Ferroelectric negative capacitance materials have now been proposed for lowering electronics energy dissipation beyond basic limitations. In this paper, we presented the analysis on the performance of negative capacitance (NC) FinFET in comparison with conventional gate dielectrics by using a separation of variables approach, which is an optimal quasi-3D mathematical model. The result has been signified steeper surface potential (ψ), lower threshold voltage (Vth), 1.2 mA of on-state current (Ion), and enhanced immunity of negative capacitance FinFET against short channel effects (SCE’s) like 35.3 mV/V of drain-induced barrier lowering (DIBL), 60 mV/dec of subthreshold swing (SS) along with smallest off state current (Ioff) among another conventional gate dielectric. Hence, NC FinFET can be a potential candidate for low power and high-performance device.

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“…A popular technique used to reduce this resistance is the self-aligned silicide ͑SALICIDE͒ process using titanium or cobalt silicide. 3 But if the SOI thickness is reduced to about 20 nm or less, it is thought that the SOI layer will be consumed to form a silicide layer, thereby greatly increasing the S/D series resistance. Therefore, a raised S/D structure, 4,5 which is formed by selective Si epitaxial growth on an S/D layer, will probably be needed in order to apply the SALICIDE process to ultrathinfilm ͑р20 nm͒ SOI substrates.…”

mentioning

confidence: 99%

Si Consumption in Selective Chemical Vapor Deposition of Tungsten Using SiH[sub 4] Reduction of WF[sub 6]

Takahashi

Takayama

2001

J. Electrochem. Soc.

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Silicon consumption in a selective tungsten chemical vapor deposition ͑SWCVD͒ process using SiH 4 reduction of WF 6 was investigated. In the SWCVD process, the Si surface was consumed through the reduction of the WF 6 until a continuous W cladding layer was formed. The dependence of Si consumption on growth temperature and impurity concentration was investigated by measuring the decrease in silicon on insulator ͑SOI͒ thickness using an ellipsometer. The consumption decreased with a decrease of the growth temperature dependent on an activation energy of 0.104 eV; the consumption increased in proportion to the phosphorus concentration, in the region where the concentration was above about 9 ϫ 10 19 cm Ϫ3 . It was demonstrated that SWCVD could be applied to fabricate a W cladding layer on the gate/source/drain regions of the fully depleted 20 nm SOI complementary metal oxide semiconductor field effect transistors ͑CMOSFETs͒. Moreover, optimizing the fabrication process to avoid excess impurity concentration in the n ϩ -S/D regions of the n-MOSFETs will make this technology suitable for use with thinner SOI devices.The selective tungsten chemical vapor deposition ͑SWCVD͒ process is a potentially advantageous way to reduce the source/drain ͑S/D͒ series resistance of ultrathin-film silicon on insulator metal oxide semiconductor field effect transistors ͑SOI MOSFETs͒ because of its small Si consumption. We have fabricated fully depleted ͑FD͒ 20 nm SOI complementary MOSFETs ͑CMOSFETs͒ using low temperature SWCVD. 1 In these FD CMOS/SOI devices, the reduction of short-channel effects was highly dependent on the thickness of the SOI. 2 However, the use of an ultrathin SOI substrate increased the S/D series resistance. A popular technique used to reduce this resistance is the self-aligned silicide ͑SALICIDE͒ process using titanium or cobalt silicide. 3 But if the SOI thickness is reduced to about 20 nm or less, it is thought that the SOI layer will be consumed to form a silicide layer, thereby greatly increasing the S/D series resistance. Therefore, a raised S/D structure, 4,5 which is formed by selective Si epitaxial growth on an S/D layer, will probably be needed in order to apply the SALICIDE process to ultrathinfilm ͑р20 nm͒ SOI substrates. Conversely, the SWCVD process can be used to deposit W film on an ultrathin SOI layer without using a raised structure. 1 There have been many investigations on the characteristics of W film, 6 the encroachment, 7-9 the interface characteristics of W and Si, 10 and the mechanism for SWCVD using either the H 2 or SiH 4 reduction of WF 6 . 11,12 However, there is another important point of view regarding deposition on ultrathin-film SOI devices. 1 It concerns the amount of Si consumed during W film growth as the SOI becomes thinner as a result of the reduction of gate length. In this paper, we describe the dependence of Si consumption on temperature and impurity concentration. ExperimentalWe used separation by implanted oxygen ͑SIMOX͒ wafers to precisely measure the difference of SOI t...

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A 0.18 μm fully depleted CMOS on 30 nm thick SOI for sub-1.0 V operation

Cited by 7 publications

References 1 publication

Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review

Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review

Mathematical Modeling and Performance Evaluation of 3D Ferroelectric Negative Capacitance FinFET

Si Consumption in Selective Chemical Vapor Deposition of Tungsten Using SiH[sub 4] Reduction of WF[sub 6]

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