A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs

Matsuzuka, Ryo; Hirose, Takahisa; Shizuku, Yuzuru; Kuroki, Nobutaka; Numa, Masahiro

doi:10.1109/iscas.2015.7169305

Cited by 29 publications

(11 citation statements)

References 8 publications

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“…The SAE signal timing is set separately for each SRAM scheme to meet the six-sigma RAPY. After the analysis for several level-shifter candidates [29]- [31], MWCMHB [29] is decided as a level-shifter design because of its low power consumption.…”

Section: Circuit-level Simulation Resultsmentioning

confidence: 99%

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

et al. 2020

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An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high-performance cache requirement in recent computing systems. The requirement of many level shifters is another drawback of the dual-rail SRAM because it degrades the energy-savings. The proposed ELS dualrail SRAM achieves energy-savings by using a low supply voltage to precharge bitlines while minimizing the performance overhead by appropriately assigning a high-supply voltage to critical circuit blocks with effective level-shifting circuits. The sense amplifier embeds a level-shifting operation, thereby operating with a high supply voltage for a fast sensing operation. The proposed dynamic output buffer resolves the potential static current problem and improves the read delay. The number of level shifters is reduced using a proposed write driver, which conducts level-shifting and write-driving simultaneously. The proposed ELS dual-rail SRAM achieves low-power operation with 71.4% power consumption compared to single-rail SRAM with 72% performance overhead in circuit-level simulation, while the previous hybrid dual-rail SRAM shows 67.8% energy consumption with 270% performance overhead. In architecture-level simulation using Gem5 simulator with SPEC2006 benchmarks, the system with the ELS dual-rail SRAM caches shows, on average, 29% performance improvement compared to that of the system with the hybrid dual-rail SRAM caches.

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Section: Circuit-level Simulation Resultsmentioning

confidence: 99%

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

et al. 2020

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“…As a result design cost and chip area found to be minimized. A level shifter with preamplifier along with an error correction circuit and also an output latch stage was proposed by Matsuzka et al proved to be dissipating large energy and have long transition time [15]. Since the circuit is based on a single transistor to help reducing the cost of the design.…”

Section: Literature Surveymentioning

confidence: 99%

High Speed Level Shifters for Low Power Applications with Reduced Size

2018

IJRTER

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-In this paper a high speed level shifter is proposed for low power applications. This circuit is a power efficient level shifter that converts low level input voltages to high level voltages as per the design requirement. The efficiency of pull up and pull down transistors are improved in the proposed method and the circuit was tested by using 180 nm CMOS technology. A unit buffer and inverter circuit was introduced to the load circuits and input buffers to have fair comparison between different structures. The overall power consumption in the proposed circuit was reduced to a minimum level by reducing the number of transistors to build a level shifter.

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“…Various hybrid LSs based on a combination of the current mirror structure and voltage latch structure are exploited in [9,10]. These LSs can successfully convert a signal from sub-threshold to nominal voltage, achieving an optimal trade-off between speed and power consumption.…”

Section: Conventional Designs and Previous Workmentioning

confidence: 99%

“…Moreover, the power consumption is inefficient due to the large short-circuit current. To solve these problems, several LSs have been investigated in [1,2,3,4,5,6,7,8,9,10]. Generally, these schemes can be summarized in three categories: the current mirror structure [1,2,3,4], the cross-coupled latch structure [5,6,7,8], and the hybrid voltage-current structure [9,10].…”

Section: Introductionmentioning

confidence: 99%

A single-supply sub-threshold level shifter with an internal supply feedback loop for multi-voltage applications

Liu

Zeng

et al. 2018

IEICE Electron. Express

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A single-supply level shifter with an internal supply feedback loop, which can shift an input signal from the sub-threshold level to the above-threshold level, is presented in this paper. This level shifter has a wider voltage conversion, less transmission delay, higher energy efficiency, and more flexibility in the physical layout than those described in previous citations. The proposed level shifter can convert a 210-mV input signal into a 1.2-V output signal across process corners with a flexible physical layout when implemented in 65-nm LP technology. For a voltage of 0.2 V, the circuit has a propagation delay of 19.4 ns, a static power dissipation of 1.84 nW, and an energy consumption per transition of 82.2 fJ for a 1-MHz input signal. Due to these excellent characteristics, the proposed design is particularly suitable for applications in multi-voltage digital systems.

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A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs

Cited by 29 publications

References 8 publications

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

High Speed Level Shifters for Low Power Applications with Reduced Size

A single-supply sub-threshold level shifter with an internal supply feedback loop for multi-voltage applications

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