An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

Abstract

An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high-performance cache requirement in recent computing systems. The requirement of many level shifters is another drawback of the dual-rail SRAM because it degrades the energy-savings. The proposed ELS dualrail SRAM achieves energy-savings by using a low supply voltage to precharge bitlines while minimizing the performance overhead by appropriately assigning a high-supply voltage to critical circuit blocks with effective level-shifting circuits. The sense amplifier embeds a level-shifting operation, thereby operating with a high supply voltage for a fast sensing operation. The proposed dynamic output buffer resolves the potential static current problem and improves the read delay. The number of level shifters is reduced using a proposed write driver, which conducts level-shifting and write-driving simultaneously. The proposed ELS dual-rail SRAM achieves low-power operation with 71.4% power consumption compared to single-rail SRAM with 72% performance overhead in circuit-level simulation, while the previous hybrid dual-rail SRAM shows 67.8% energy consumption with 270% performance overhead. In architecture-level simulation using Gem5 simulator with SPEC2006 benchmarks, the system with the ELS dual-rail SRAM caches shows, on average, 29% performance improvement compared to that of the system with the hybrid dual-rail SRAM caches.

Process Tolerant and Power Efficient SRAM Cell for Internet of Things Applications

“…The conventional cells such as 6 T cell and 8 T cell are industry standard architectures which normally used as the reference to benchmark the SRAM performance. The researchers have proposed many budding SRAM cell topologies with enhanced outcome while comparing with these traditional topologies [11][12][13][14][15]. However, in common these cells suffer from conflict between read and operations, degraded stability, half select issue, write failures etc.…”

“…The researchers have also forecasted that the process variation may limit the required minimum voltage for the write and read operations. There have been so many improved SRAM cells proposed by researchers [11][12][13][14][15] to enhance the outcomes against conventional 6 T cell.…”

“…The main generic challenges of these SRAM memory are high power consumption, degraded stability, leakage current, short channel effects (SCEs). Over the years, many researchers have suggested and developed many different approaches and techniques to lower the overall power of cache memory [9,10] e.g., differential operation, loop cutting, staff effect, decoupled read circuit, power gating, single bit line operation, lower the supply voltage and schmitt trigger approach [11][12][13][14][15]. The SRAM cells with separate write and read circuits improve significant stability [16,17].…”

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

“…The leakage power of the overall chip is increased due to the large number of cells in standby mode, whereas the lower power of the SRAM cell can be achieved using the supply voltage scaling technique [4]. Still, the reduction in supply voltage drastically reduces the stability, which increases the occurrence of errors in read, write, and hold operations [5,6]. Therefore, we need to design a circuit with proper device constraints and aspect ratio to mitigate the failure rate [7].…”

A High-Density Memory Design Based on Self-Aligned Tunneling Window for Large-Capacity Memory Application

“…However, the conventional 6T-SRAM has encountered severe challenges in the implementation of large-capacity memory due to the large cell size (~80 F 2 -120 F 2 ). A memory technology with comparable speed but higher density has been urged by the development of on-chip memory [1][2][3]. In the past fifty years, various new devices have become the driving force for the development of the semiconductor industry.…”