Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Gupta, Neha; Shah, Ambika Prasad; Khan, Sajid; Vishvakarma, Santosh Kumar; Waltl, Michael; Girard, Patrick

doi:10.3390/electronics10141718

Cited by 6 publications

(4 citation statements)

References 26 publications

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“…The proposed cell's average leakage power is the lowest at all process corners due to the stack effect induced by the tail transistors. The leakage power increases as the temperature increases [33]. The temperature variation would usually affect the performance and the speed of the cell [34].…”

Section: Pvt Variation Of Leakage Power Analysismentioning

confidence: 99%

Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read–Write Assist (DARWA) Technique for Low-Power Applications

Thirugnanam¹,

Soong

Prabhu

et al. 2023

Sensors

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The need for power-efficient devices, such as smart sensor nodes, mobile devices, and portable digital gadgets, is markedly increasing and these devices are becoming commonly used in daily life. These devices continue to demand an energy-efficient cache memory designed on Static Random-Access Memory (SRAM) with enhanced speed, performance, and stability to perform on-chip data processing and faster computations. This paper presents an energy-efficient and variability-resilient 11T (E2VR11T) SRAM cell, which is designed with a novel Data-Aware Read–Write Assist (DARWA) technique. The E2VR11T cell comprises 11 transistors and operates with single-ended read and dynamic differential write circuits. The simulated results in a 45 nm CMOS technology exhibit 71.63% and 58.77% lower read energy than ST9T and LP10T and lower write energies of 28.25% and 51.79% against S8T and LP10T cells, respectively. The leakage power is reduced by 56.32% and 40.90% compared to ST9T and LP10T cells. The read static noise margin (RSNM) is improved by 1.94× and 0.18×, while the write noise margin (WNM) is improved by 19.57% and 8.70% against C6T and S8T cells. The variability investigation using the Monte Carlo simulation on 5000 samples highly validates the robustness and variability resilience of the proposed cell. The improved overall performance of the proposed E2VR11T cell makes it suitable for low-power applications.

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Section: Pvt Variation Of Leakage Power Analysismentioning

confidence: 99%

Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read–Write Assist (DARWA) Technique for Low-Power Applications

Thirugnanam¹,

Soong

Prabhu

et al. 2023

Sensors

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“…In energy-efficiency memory array architectures, 22,23 the on-chip adaptive power supply circuit scheme is used to reduce the overall power consumption of the array structure in other operating cycles without considering the storage bit identity. However, in this type of memory array architecture, due to the static function of the voltage level generation circuit block, a significant reduction in static and leakage power consumption of the memory array will not be achieved.…”

Section: Description Of the Proposed Memory Array With Online Adaptiv...mentioning

confidence: 99%

“…To achieve a memory array architecture with a simple hardware layout scheme, the traditional hierarchical memory array architecture structure has been used. On the other hand, in the proposed memory array structure, unlike the conventional array architecture with the on-chip adaptive voltage level generation block, 22,23 the adaptive voltage level is determined based on a data-dependent real-time algorithm. In the following subsections, the proposed off-chip adaptive voltage level generation block and the algorithm details are examined.…”

Section: Description Of the Proposed Memory Array With Online Adaptiv...mentioning

confidence: 99%

One‐sided 10T static‐random access memory cell for energy‐efficient and noise‐immune internet of things applications

Darabi

Salehi

Abiri

2022

Circuit Theory & Apps

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This paper presents a one‐sided 10‐transistors static‐random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy‐efficient SRAM cells are necessary to raise the battery lifetime. The bit‐cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate‐wrap‐around (GWA) carbon nanotube (CNT)‐gate‐diffusion input (GDI) technique and only one‐bit line to perform both read and write operations to minimize active power consumption. The proposed bit‐cell uses a transmission gate network and write‐assist schemes to significantly improve the write‐ability and stack read‐decoupling technique to enhance hold‐/read‐stability. Moreover, a memory mini‐array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write‐ and read‐yield parameters for the proposed SRAM bit‐cell are about 22% and 13% better than counterpart bit‐cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit‐cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit‐cell in the real‐world application, a memory array architecture with an online (or off‐chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy‐efficient and noise‐immunity IoT platforms.

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“…16. With the increase of temperature, the static power normally increases [37]. The variation of temperature will affect the speed of the cell [38].…”

Section: Impact Of Pvt Variation On Static Powermentioning

confidence: 99%

Process Tolerant and Power Efficient SRAM Cell for Internet of Things Applications

Sargunam¹,

Soong²,

Prabhu³

et al. 2022

Computers, Materials &Amp; Continua

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The use of Internet of Things (IoT) applications become dominant in many systems. Its on-chip data processing and computations are also increasing consistently. The battery enabled and low leakage memory system at subthreshold regime is a critical requirement for these IoT applications. The cache memory designed on Static Random-Access Memory (SRAM) cell with features such as low power, high speed, and process tolerance are highly important for the IoT memory system. Therefore, a process tolerant SRAM cell with low power, improved delay and better stability is presented in this research paper. The proposed cell comprises 11 transistors designed with symmetric approach for write operations and single ended circuit for read operations that exhibits an average dynamic power saving of 43.55% and 47.75% for write and 35.59% and 36.56% for read operations compared to 6 T and 8 T SRAM cells. The cell shows an improved write delay of 26.46% and 37.16% over 6 T and 8 T and read delay is lowered by 50.64% and 72.90% against 6 T and 10 T cells. The symmetric design used in core latch to improve the write noise margin (WNM) by 17.78% and 6.67% whereas the single ended separate read circuit improves the Read Static Noise Margin (RSNM) by 1.88x and 0.33x compared to 6 T and 8 T cells. The read power delay product and write power delay product are lower by 1.94x, 1.39x and 0.17x, 2.02x than 6 T and 8 T cells respectively. The lower variability from 5000 samples validates the robustness of the proposed cell. The simulations are carried out in Cadence virtuoso simulator tool with Generic Process Design Kit (GPDK) 45 nm technology file in this work.

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Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Cited by 6 publications

References 26 publications

Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read–Write Assist (DARWA) Technique for Low-Power Applications

Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read–Write Assist (DARWA) Technique for Low-Power Applications

One‐sided 10T static‐random access memory cell for energy‐efficient and noise‐immune internet of things applications

Process Tolerant and Power Efficient SRAM Cell for Internet of Things Applications

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