A 0.2V 0.44 ¿W 20 kHz Analog to Digital ¿¿ Modulator with 57 fJ/conversion FoM

A 0.2V, 7.5 μW, 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOS

“…Furthermore, multi-bit quantization can be incorporated without any performance degradation from a feedback DAC. A 0.2 V FDSM with an SNR of 47.4 dB, an SNDR of 44.2 dB, and a figure-of-merit (FoM) of 57 fJ/conversion was demonstrated in [4]. In this work, we show that much higher SNR and SNDR are achievable by increasing power consumption, for the same exceedingly low supply voltage, at an almost constant FoM.…”

“…This issue has been much alleviated, compared to [4], by a custom flipflop redesign optimized for a very low supply voltage, and by increasing the steepness of the signals at the flip-flop inputs by inserting buffers between RVCO and flip-flops.…”

“…The differential, larger FDSM has an area of 160 × 85 µm 2 (photograph not included, as metal fillings hide all details). All measurements are taken with a power supply of 0.2 V. To increase SNR the power consumed by the RVCOs has been increased by a factor 6 to 3.0µW, compared to [4]. An additional 3 dB SNR improvement is yielded by the differential topology.…”

“…A digital differentiator follows the quantizer, which means that the input signal is now found at the output in digital form, while quantization noise is high-pass filtered, as in a traditional Σ∆ modulator. In a single-bit FDSM, the differentiator consists of one flip-flop as delay cell, and a XOR gate performing a modulo-2 subtraction [4]. Since the RVCO inverters and all digital circuitry are capable of weak-inversion operations, a supply voltage well below MOS threshold voltages is possible [5].…”

“…To improve the performance of the FDSM, compared to [4], the noise floor must be lowered. There are several potential noise sources in a FDSM, but the primary source is the phase noise in the RVCO.…”