A 0.3 mW 2.4 GHZ LOW POWER LOW NOISE AMPLIFIER USING FORWARD BODY BIAS TECHNIQUE FOR WIRELESS SENSOR ARD BODY BIAS TECHNIQUE FOR WIRELESS SENSOR NETWORK

Azizan, A.; Murad, S. A. Z.

doi:10.11113/jt.v78.4172

Cited by 4 publications

(3 citation statements)

References 19 publications

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“…The design approached is based on previous published technique which is forward body bias [14] and single forward body bias technique [19][20]. The proposed LNA is shown in Figure 3.…”

Section: Lna Circuit Designmentioning

confidence: 99%

Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor networks using 0.13-m technology

Murad

Azizan

Hasan³

2020

Bulletin EEI

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This paper describes the design topology of a ultra-low power low noise amplifier (LNA) for wireless sensor network (WSN) application. The proposed design of ultra-low power 2.4 GHz CMOS LNA is implemented using 0.13-μm Silterra technology. The LNA benefits of low power from forward body bias technique for first and second stages. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The simulation results show that the total power consumed is only 0.45 mW at low supply voltage of 0.55 V. The power consumption is decreased about 36% as compared with the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input third order intercept point (IIP3) of -2 dBm are achieved. The input return loss (S11) and the output return loss (S22) is -17.6 dB and -12.3 dB, respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1.

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“…The design approached is based on previous published technique which is forward body bias [14] and single forward body bias technique [19][20]. The proposed LNA is shown in Figure 3.…”

Section: Lna Circuit Designmentioning

confidence: 99%

Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor networks using 0.13-m technology

Murad

Azizan

Hasan³

2020

Bulletin EEI

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“…As a result, power supply rejection ratio (PSRR) is an important parameter of linear regulators. Besides that, LDO linear voltage regulators are mostly used in integrated circuit (IC) design due to their performance, low cost and simplicity [10].…”

Section: Introductionmentioning

confidence: 99%

A Very Low-Dropout Voltage Regulator in 0.18-M Cmos Technology for Power Management System

et al. 2020

Self Cite

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This paper proposes the design of a very low-dropout (LDO) voltage regulator in 0.18-mm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results show that the proposed LDO is capable to operate from a supply voltage of 1.7-2.0 V with a low dropout voltage of 19.3 mV at a maximum 50 mA load current to regulate output voltage 1.5 V. The active chip is 2.96 mm2 in size. The performance of the proposed LDO is suitable to enhance power management for system on chip (SoC) applications.

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“…The switching technique will leads to unnecessary increase in area and cost [7]. In the case of LNA, noise figure are a vital consideration as the LNA receives a very weak input signal [8]. While the LNA is an active block in receiving chain, the noise figure sets at the LNA stages are the minimum value of noise at the entire system.…”

Section: Introductionmentioning

confidence: 99%

A concurrent dual-band CMOS low noise amplifier at 2.4/5.2 GHz for WLAN applications

Murad

Hasan

Azizan

et al. 2019

IJEECS

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<span>This paper presents a concurrent dual-band CMOS low noise amplifier (LNA) at operating frequency of 2.4 GHz and 5.2 GHz for WLAN applications. The proposed LNA employed cascode common source to obtain high gain using 0.13-µm CMOS technology. The concurrent dual-band frequencies are matched using LC network band-pass and band-stop notch filter at the input and output stages. The filters help to shape the frequency response of the proposed LNA. The simulation results indicate that the LNA achieves a forward gain of 21.8 dB and 14.22 dB, input return loss of -18 dB and -14 dB at 2.4 GHz and 5.2 GHz, respectively. The noise figure of 4.1 dB and 3.5 dB with the input third-order intercept points 7 dBm and 10 dBm are obtained at 2.4 GHz and 5.2 GHz, respectively. The LNA dissipates 2.4 mW power at 1.2 V supply voltage with a chip size of 1.69 mm2.</span>

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A 0.3 mW 2.4 GHZ LOW POWER LOW NOISE AMPLIFIER USING FORWARD BODY BIAS TECHNIQUE FOR WIRELESS SENSOR ARD BODY BIAS TECHNIQUE FOR WIRELESS SENSOR NETWORK

Cited by 4 publications

References 19 publications

Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor networks using 0.13-m technology

Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor networks using 0.13-m technology

A Very Low-Dropout Voltage Regulator in 0.18-M Cmos Technology for Power Management System

A concurrent dual-band CMOS low noise amplifier at 2.4/5.2 GHz for WLAN applications

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