A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation

Moon, Joung Wook; Kim, Sung Geun; Kwon, Dong-Hee; Choi, Woo Young

doi:10.1109/cicc.2014.6946100

Cited by 12 publications

(4 citation statements)

References 7 publications

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“…The proposed DPLL shows the best rms jitter. Also, the figure of merit (FOM) achieved with the proposed DPPL is the same as that achieved with the analogue PLL [8].…”

Section: Test Resultsmentioning

confidence: 99%

Near threshold voltage digital PLL using low voltage optimised blocks for AR display system

Jun

Lee

Kim

2020

IET Circuits, Devices & Systems

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In this work, a digital phase-locked loop (DPLL) is proposed for the low power and stable operation in an augmented reality (AR) display system. The AR display system which needs the ultra-low power consumption adopts the near-threshold voltage (NTV) operation in both digital and analogue blocks. The NTV region has the advantage of small power dissipation with low-supply voltage. However, it suffers from performance degradation due to a large delay, slow transition time, and small dynamic voltage range. To achieve the optimised power efficiency and stable performance, the dynamic time-to-digital converter and the low voltage optimised digitally controlled oscillator are applied in the proposed DPLL. In addition, the forward body biasing scheme is used to increase the operation frequency for the sigma-delta modulator block. The proposed DPLL is fabricated using 65 nm CMOS technology and shows a current consumption of 160 μA at a voltage of 0.55 V. In addition, the jitter characteristic shows 6.7 ps rms jitter and 50 ps peak to peak jitter at 480 MHz.

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“…The proposed DPLL shows the best rms jitter. Also, the figure of merit (FOM) achieved with the proposed DPPL is the same as that achieved with the analogue PLL [8].…”

Section: Test Resultsmentioning

confidence: 99%

Near threshold voltage digital PLL using low voltage optimised blocks for AR display system

Jun

Lee

Kim

2020

IET Circuits, Devices & Systems

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“…However, this is a huge challenge for mixed-signal circuits such as Phase-Locked Loops (PLLs) [48] . As critical modules that affect PLL performance, Voltage-Controlled Oscillators (VCOs) and Charge Pumps (CPs) have become difficult issues for PLL designs under low voltage [49][50][51][52] . Reference [49] proposed a Feed-forward Ring VCO (FRVCO) for low voltage PLL to effectively compensate for frequency fluctuations caused by power supply noise by adjusting the drive strength ratio between the FRVCO direct path and the feed-forward path.…”

Section: Related Researchesmentioning

confidence: 99%

“…A novel CP structure was introduced in Ref. [51] to realize the NTV PLL, achieving excellent matching characteristics of up/down currents and higher output resistance, effectively alleviating the impact of CP current changes with VCO control voltages. In Ref.…”

Section: Related Researchesmentioning

confidence: 99%

Near-Threshold Wide-Voltage Design Review

Zhao

Yang

Chen

et al. 2023

Tsinghua Sci. Technol.

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This paper presents a comprehensive review of near-threshold wide-voltage designs on memory, resilient logic designs, low voltage Radio Frequency (RF) circuits, and timing analysis. With the prosperous development of wearable applications, low power consumption has become one of the primary challenges for IC designs. To improve the power efficiency, the prefer scheme is to operate at an ultra low voltage of Near Threshold Voltage (NTV). For the performance variation and degradation, a self-adaptive margin assignment technique is proposed in the low voltage. The proposed technique tracks the circuit states in real time and dynamically allocates voltage margins, reducing the minimum supply voltage and achieving higher energy efficiency. The self-adaptive margin assignment technique can be used in Static Random Access Memory (SRAM), digital circuits, and analog/RF circuits. Based on the self-adaptive margin assignment technique, the minimum voltage in the 40 nm CMOS process is reduced to 0.6 V or even lower, and the energy efficiency is increased by 3-4 times.

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“…In some case, if the divider operation frequency is not so high that it can operate at lower supply voltage, the current-reuse technique [71,72] can be used to reduce power by stacking the VCO with the high-frequency prescaler and the MMD between the supply and ground, as shown in Fig. 12(d).…”

Section: Power Reduction Techniquesmentioning

confidence: 99%

CMOS analog and mixed-signal phase-locked loops: An overview

Zhang¹

2020

J. Semicond.

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CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the system-on-chips (SoC) as the clock generator or frequency synthesizer. This paper presents an overview of the AMS-PLL, including: 1) a brief introduction of the basics of the charge-pump based PLL, which is the most widely used AMS-PLL architecture due to its simplicity and robustness; 2) a summary of the design issues of the basic CPPLL architecture; 3) a systematic introduction of the techniques for the performance enhancement of the CPPLL; 4) a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter (< 100 fs) with lower power consumption compared with the CPPLL, including the injection-locked PLL (ILPLL), sub-sampling (SSPLL) and sampling PLL (SPLL); 5) a discussion about the consideration of the AMS-PLL architecture selection, which could help designers meet their performance requirements.

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A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation

Cited by 12 publications

References 7 publications

Near threshold voltage digital PLL using low voltage optimised blocks for AR display system

Near threshold voltage digital PLL using low voltage optimised blocks for AR display system

Near-Threshold Wide-Voltage Design Review

CMOS analog and mixed-signal phase-locked loops: An overview

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