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Abstract-This paper presents an inductorless 8-Gb/s adaptive passive equalizer with low-power consumption and small chip area. The equalizer has a tunable RC filter which provides high-frequency gain boosting and a limiting amplifier that restores the signal level from the filter output. It also includes a feedback loop which automatically adjusts the filter gain for the optimal frequency response. The equalizer fabricated in 0.18-µm CMOS technology can successfully equalize 8-Gb/s data transmitted through up to 50-cm FR4 PCB channels. It consumes 6.75 mW from 1.8-V supply voltage and occupies 0.021 mm 2 of chip area.

An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm 2 and consumes 88 W at 0.4-V supply for 200-MHz operation.