A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET

Im, Jungho; Chen, S.; Dave, Freitas; Chou, Adam; Zhou, Lei; Ian, Zhuang; Cronin, Tim; Mahashin, David; Lin, Winson; Chan, Kok Lim; Zhao, Huandong; Tan, Kee Hian; Bekele, Ade; Turker, Didem; Upadhyaya, Parag; Frans, Yohan; Chang, Ken

doi:10.1109/vlsic.2018.8502275

Cited by 4 publications

(3 citation statements)

References 2 publications

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“…As can be easily perceived, the shorter the BM-CDR locking time, the less throughput hit that occurs due to the frame preamble. Moreover, as current and future network protocols feature short data-bursts or radio on/off functionality, BM-CDR devices with ns-scale settling are being actively developed supporting rates up-to or above 25Gb/s in order to keep pace with the respective protocols' lanerates [30], [38][36], [39].To achieve this datarate scaling researchers have relied on different techniques and technologies, such as advanced FinFet CMOS platforms, additional equalizers that compensate the bandwidth limitations introduced by optical (de)modulators, or even clean clock sources originating from an external source or PLL. On the other hand, in order to decrease the CDR locking time, additional circuits are added, such as two types of phase detectors towards satisfying the contradicting requirements of fast-locking and stable, low jitter operation when phase lock is obtained [30], [38].…”

Section: Principle Of Operation and Deployment Of Ops In DC Networkmentioning

confidence: 99%

“…a burst-mode phase detector and a traditional bang-bang phase detector, both requirements can be achieved in one design, while a finite state machine controls which phase detector is active. Finally, by introducing metastability detection [39], the meta-stable conditions, that arise due to the uncorrelation of the recovered clock and the incoming burst, are avoided and the maximum lock time is reduced.…”

Section: Principle Of Operation and Deployment Of Ops In DC Networkmentioning

confidence: 99%

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End-to-End 1024-Port Optical Packet Switching With 25 Gb/s Burst-Mode Reception for Data Centers

et al. 2021

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Despite the fact that Optical Packet Switching (OPS) emerges as a promising solution for future Data Center (DC) networks, towards increasing capacity and radix, while retaining sub-μs latency performance, the requirement for ultra-fast burst-mode reception has been a serious restraining factor. We attempt to overcome this limitation and demonstrate, for the first time to our knowledge, an end-to-end optical packet switch link through the 1024-port 25.6Tb/s Hipoλaos OPS, featuring burst-mode reception with <50ns locking time. The switch performance for unicast traffic is evaluated via Bit-Error-Rate measurements and error-free performance at 10 -9 is reported for all validated port-combinations, with a mean power penalty of 2.88dB. Moreover, multicast flows from two different ports of the switch were successfully received validating the architecture's credentials for efficient multicast packet delivery. Taking one step further towards a realistic evaluation of an OPS-enabled DC, a simulation analysis was conducted, proving that low-latency performance, including the burst-mode reception time-overhead, can be successfully realized in a Hipoλaos-switched DC with up-to 100% throughput for a variety of traffic profiles.

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Section: Principle Of Operation and Deployment Of Ops In DC Networkmentioning

confidence: 99%

Section: Principle Of Operation and Deployment Of Ops In DC Networkmentioning

confidence: 99%

End-to-End 1024-Port Optical Packet Switching With 25 Gb/s Burst-Mode Reception for Data Centers

et al. 2021

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“…High-speed wireline communications have developed explosively with the growing demand for big data, cloud computing, and internet of things (IoT) applications [1]- [7]. The required data rate is 25 GB/s for a variety of communication standards, such as OIF CEI-25G-LR, CEI-28G-VSR and IEEE802.3cp [8]- [10]. For multi-standard applications, continuous-rate CDR circuits have become the focus of research [11]- [15].…”

Section: Introductionmentioning

confidence: 99%

A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO

Pan

Shi

Zhao

et al. 2022

IEICE Electron. Express

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This paper presents a 21.3-24.5 Gb/s phase locked loop (PLL)-based reference-less clock and data recovery (CDR) circuit. A cascode-coupled technique is used in the design of the quadrature voltagecontrolled oscillator (VCO), which eliminates the phenomenon of dualmode oscillation, provides a stable phase sequence for frequency acquisition and ensures the correct loop locking. The dual loop topology is adopted to realize a wide frequency acquisition range and an autonomous transition from frequency locking to phase locking, while the PLL-based structure brings in an excellent jitter performance. When the data rate of the input PRBS9 is 24.5 Gb/s, the measured peak-to-peak jitter and the rootmean-square (RMS) jitter of the recovered clock are 2.7 ps and 0.39 ps respectively, and the peak-to-peak jitter and the RMS jitter of the recovered data are 7.7 ps and 1.5 ps respectively. Implemented in 55-nm CMOS technology, the CDR circuit occupies a core area of 0.7mm 2 and consumes 170mW at 1.2V power supply.

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A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET

Zheng

Chou

et al. 2021

IEEE J. Solid-State Circuits

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A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET

Cited by 4 publications

References 2 publications

End-to-End 1024-Port Optical Packet Switching With 25 Gb/s Burst-Mode Reception for Data Centers

End-to-End 1024-Port Optical Packet Switching With 25 Gb/s Burst-Mode Reception for Data Centers

A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET

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