A 0.5-/spl mu/m, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor

Miyakawa, T.; Itoh, Y.; Takeuchi, Yoshinori; Ogiwara, R.; Doumae, Sumiko; Takenakal, H.; Kunishima, I.; Shuto, S.; Hidaka, O.; Ohtsuki, Satoshi; Tanaka, S.

doi:10.1109/4.839914

Cited by 21 publications

(6 citation statements)

References 2 publications

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“…1T-SRAM with adiabatic driving Figure 4 is our previously proposed the basic structure for a memristor NMOS storage cell [13]. This storage cell is a similar 1T1C circuit using FRAM [15] or capacitor [16]. Figure 5(a) illustrates the proposed timing diagram in order to achieve optimum output signal and low-power dissipation.…”

Section: B Spice Model Of Hp's Memristormentioning

confidence: 98%

A low-power sense amplifier for adiabatic memory using memristor

Urata

Takahashi

Sekine

et al. 2012

2012 IEEE Asia Pacific Conference on Circuits and Systems

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Section: B Spice Model Of Hp's Memristormentioning

confidence: 98%

A low-power sense amplifier for adiabatic memory using memristor

Urata

Takahashi

Sekine

et al. 2012

2012 IEEE Asia Pacific Conference on Circuits and Systems

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Section: Proposed 1t2c Fecap-based X(n)or Logic Operationmentioning

confidence: 99%

“…For the traditional SA mode, the output of the SA will be fed back to the memory cell. As shown in Figure 9, when the read pulse on BL is pulled down, the rewriting of the data in the FeCAP is completed with the assistance of the latch SA [34]. However, for the X(N)OR mode, two rows of data stored on the same BL (or PL) are simultaneously read out, and the data of the cells cannot be written back in time.…”

Section: Two-step Write-back Circuitmentioning

confidence: 99%

A 1T2C FeCAP-Based In-Situ Bitwise X(N)OR Logic Operation with Two-Step Write-Back Circuit for Accelerating Compute-In-Memory

et al. 2021

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Ferroelectric capacitors (FeCAPs) with high process compatibility, high reliability, ultra-low programming current and fast operation speed are promising candidates to traditional volatile and nonvolatile memory. In addition, they have great potential in the fields of storage, computing, and memory logic. Nevertheless, effective methods to realize logic and memory in FeCAP devices are still lacking. This study proposes a 1T2C FeCAP-based in situ bitwise X(N)OR logic based on a charge-sharing function. First, using the 1T2C structure and a two-step write-back circuit, the nondestructive reading is realized with less complexity than the previous work. Second, a method of two-line activation is used during the operation of X(N)OR. The verification results show that the speed, area and power consumption of the proposed 1T2C FeCAP-based bitwise logic operations are significantly improved.

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“…This overlap degrades the effective cell signal margin between the bitline voltage and the reference bitline bias VrefBL of Fig. 1(b), if the conventional constant reference bitline bias design using MOS capacitor [8] is applied. One solution to overcome this problem is the introduction of ferroelectric capacitor as reference cell [9] since the reference cell signal also changes with temperature variation.…”

Section: Introductionmentioning

confidence: 99%

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs

Ogiwara

Takashima

Doumae

et al. 2015

IEEE J. Solid-State Circuits

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This paper presents highly reliable reference bitline bias designs for 64 Mb and 128 Mb chain FeRAM™. The hysteresis shape deformation of ferroelectric capacitor due to temperature variation causes cell signal level shifts of both "1" and "0" data. The reference bitline bias of 64 Mb chip is designed to keep intermediate value of "1" and "0" data at any operating temperatures from C to 85 C by introducing a modified band-gap reference circuit with 3 bit temperature coefficient trimmers and 6 bit digital-to-analog converter (DAC) using laser fuses. The measured result shows the improvement of tail-to-tail cell signal windows by 22 mV. Moreover, a new reference bias circuit called the "elevator circuit" with 3 bit temperature coefficient trimmers using ferroelectric fuses installed in a 128 Mb chip compensates array operating voltage VAA fluctuation as well as temperature variation. The elevator circuit enables the temperature dependency control at low external VDD of 1.8 V. This improves cell signal window by 40 mV. The elevator circuit also varies reference bitline bias with array operating voltage VAA variation, resulting in improvement of cell signal windows by 44 mV in the range of 1.5 V 0.2 V VAA.

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A 0.5-/spl mu/m, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor

Cited by 21 publications

References 2 publications

A low-power sense amplifier for adiabatic memory using memristor

A low-power sense amplifier for adiabatic memory using memristor

A 1T2C FeCAP-Based In-Situ Bitwise X(N)OR Logic Operation with Two-Step Write-Back Circuit for Accelerating Compute-In-Memory

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs

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