A 1T2C FeCAP-Based In-Situ Bitwise X(N)OR Logic Operation with Two-Step Write-Back Circuit for Accelerating Compute-In-Memory

Abstract

Ferroelectric capacitors (FeCAPs) with high process compatibility, high reliability, ultra-low programming current and fast operation speed are promising candidates to traditional volatile and nonvolatile memory. In addition, they have great potential in the fields of storage, computing, and memory logic. Nevertheless, effective methods to realize logic and memory in FeCAP devices are still lacking. This study proposes a 1T2C FeCAP-based in situ bitwise X(N)OR logic based on a charge-sharing function. First, using the 1T2C structure and a two-step write-back circuit, the nondestructive reading is realized with less complexity than the previous work. Second, a method of two-line activation is used during the operation of X(N)OR. The verification results show that the speed, area and power consumption of the proposed 1T2C FeCAP-based bitwise logic operations are significantly improved.

Methodology for Testing Key Parameters of Array-Level Small-Area Hafnium-Based Ferroelectric Capacitors Using Time-to-Digital Converter and Capacitance Calibration Circuits

“…The test results are shown in Figure 3b. The modeling approach in this work is consistent with [19]. C1 and R1 are parasitic parameters of the ferroelectric capacitor, where Vm represents the non-linear capacitance.…”

“…The amount of bound charge is significantly larger than the accumulated charge. For example, a 100 µm 2 The modeling approach in this work is consistent with [19]. C1 and R1 are parasitic parameters of the ferroelectric capacitor, where Vm represents the non-linear capacitance.…”

NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors

“…In charge-based memory, although SRAM is very fast (~ 1 ns) and DRAM has high density, they contain volatile memory devices, and hence have high energy needs. Moreover, SRAM-based LIM suffers from chip area overhead because more transistors than in the conventional 6 T SRAM cells are required for computing operations 15 , 16 . Likewise, DRAM-based LIM has the challenges of area and yield due to the limitation of the cell structure 16 – 18 .…”

“…Moreover, SRAM-based LIM suffers from chip area overhead because more transistors than in the conventional 6 T SRAM cells are required for computing operations 15 , 16 . Likewise, DRAM-based LIM has the challenges of area and yield due to the limitation of the cell structure 16 – 18 . NAND/ NOR flash memory with a charge-trapping layer can store data long-term.…”