A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

Inti, Rajesh; Yin, Wenjing; Elshazly, Amr; Sasidhar, N.; Hanumolu, Pavan Kumar

doi:10.1109/jssc.2011.2168872

Cited by 67 publications

(27 citation statements)

References 13 publications

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“…The SRCG creates a clocklike periodic signal by dividing a random NRZ signal with a fixed transition density [5]. This SRCG technique can be utilized for frequency acquisition in any real-world application provided that the transition density is time-invariant, e.g., the transition densities of 8B/10B and 64B/66B encodings are 0.6116 and 0.5075, respectively.…”

Section: Discussionmentioning

confidence: 99%

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Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator

Han

Yang

Bae

2012

IEEE Trans. Circuits Syst. II

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This brief presents a theoretical analysis of the stochastic reference clock generator (SRCG), which creates a clocklike periodic signal from a random nonreturn-to-zero data sequence. The output of the SRCG can be utilized as a reference clock for frequency acquisition in dual-loop clock-and-data recovery circuits. A frequency-locked loop (FLL) subsequent to the SRCG guides the voltage-controlled oscillator frequency into the pull-in range of the phase-locked loop while suppressing the high-frequency phase noise of the SRCG. The phase noise and frequency offset of the SRCG-FLL pair are analyzed. The validity of the theoretical analysis is supported by results taken from a test chip.Index Terms-Data divider, frequency-locked loop (FLL), phase noise, referenceless clock-and-data recovery (CDR).

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Section: Discussionmentioning

confidence: 99%

“…7(a) [5]. Because the transfer function is linear over the entire range of frequencies as shown in Fig.…”

Section: A Frequency Offsetmentioning

confidence: 99%

Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator

Han

Yang

Bae

2012

IEEE Trans. Circuits Syst. II

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“…The CDR circuit is an important block for optical and electrical communications [12]. It is used to recover and retime the required clock from data.…”

Section: Clock and Data Recoverymentioning

confidence: 99%

A 1.248 Gb/s - 2.918 Gb/s Low-Power Receiver for MIPI-DigRF M-PHY with a Fast Settling Fully Digital Frequency Detection Loop in 0.11 ㎛ CMOS

Kim¹,

Lee²,

Park³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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“…Often, a second-order loop has to be implemented to decrease any frequency offset between transmitter clock and reference in the receiver complicating CDR design [1]. Without a reference, receiver clock still can be recovered at the cost of complexity in the design, area, and power [2].…”

Section: Introductionmentioning

confidence: 99%

A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS

Lee

Kim

Son

et al. 2014

IEICE Electron. Express

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This paper presents a low-power half-rate clock-embedded transceiver architecture that employs quarter-rate multiplexing/de-multiplexing circuit technique, low-Vdd current-mode driver topology embedding halfrate clock, and multi-functional injection-locked oscillator (ILRO) for a digital clock and data recovery (CDR) design. The whole transceiver circuit was simulated in 65 nm CMOS process and its feasibility was proved successfully operating at 10 Gb/s across a band-limited channel. The achievable power efficiencies of the receiver and transceiver were 0.7 mW/Gb/s and 1.1 mW/Gb/s respectively.

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A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

Cited by 67 publications

References 13 publications

Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator

Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator

A 1.248 Gb/s - 2.918 Gb/s Low-Power Receiver for MIPI-DigRF M-PHY with a Fast Settling Fully Digital Frequency Detection Loop in 0.11 ㎛ CMOS

A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS

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