A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization

Kao, Chen-Che; Hsieh, S. T.; Hsieh, Chih-Cheng

doi:10.1109/asscc.2017.8240254

Cited by 5 publications

(6 citation statements)

References 10 publications

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“…When input voltage is low, the pulling down of cell II will be slow. Compared with the delay cell II [12] , the inserted inverter in delay cell I increases the reset speed. The option is that four stages of the delay cell I are to be used in the proposed scheme for quicker comparison.…”

Section: Vco-based Comparator Design and Offset Considerationmentioning

confidence: 99%

“…Compared with the DFF-based PD in Ref. [12], it needn't wait for a slower edge. Therefore, it increases the speed of the comparator.…”

Section: Vco-based Comparator Design and Offset Considerationmentioning

confidence: 99%

“…For a voltage-domain comparator such as a double-tail comparator or strong-arm comparator, whose noise reduction relies on brute-force analog scaling, it requires four times the power to halve the input-referred noise [8] . Alternatively, time-domain comparators, which show good potential in power efficiency and scalability, attract attention due to their digital nature and more choices for lower noise such as VTC-based [9] , VCDL-based [10] , oscillator collapsebased [11] and VCO-based [12,13] . The last type gains much favor under its noise-adaptive characteristic.…”

Section: Introductionmentioning

confidence: 99%

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A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows

et al. 2020

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This paper proposes a technique that uses the number of oscillation cycles (NOC) of a VCO-based comparator to set multiple adaptive bypass windows in a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The analysis of the number of bit cycles, power and static performance shows that three adaptive bypass windows reduce power consumption, and decrease DNL and have similar INL, compared with the SAR ADC without bypass windows. In addition, a 1-bit split-and-recombination redundancy technique and a general bypass logic digital error correction method are proposed to address the settling issues and optimize the size of the bypass window. This design is implemented in 40 nm CMOS technology. The conversion frequency of the ADC reaches up to 30 MS/s. The ADC achieves an SFDR of 85.35 dB and 11.12-bit ENOB with Nyquist input, consuming 380 μW, down from 427 μW without multiple adaptive bypass windows, at a 1.1 V supply, resulting in a figure of merit (FoM) of 5.69 fJ/conversion-step.

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Section: Vco-based Comparator Design and Offset Considerationmentioning

confidence: 99%

“…Compared with the DFF-based PD in Ref. [12], it needn't wait for a slower edge. Therefore, it increases the speed of the comparator.…”

Section: Vco-based Comparator Design and Offset Considerationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows

et al. 2020

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“…To improve the energy efficiency and resolution of SAR ADC, researches focused on digitalto-analog converter (DAC) switching scheme and comparator have been developed [4][5][6][7][8][9][10][11][12][13][14]. Many energy-efficient DAC switching schemes have been developed to reduce the switching energy during SAR conversion [4,[14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

A Time-Domain Comparator Based Skipping-Window SAR ADC

Xie¹,

Ren²,

Zhou³

et al. 2021

Computers, Materials &Amp; Continua

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This paper presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for low-power applications. To improve the overall energy-efficiency, a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator, which can provide not only the polarity of the input, but also the amount information of the input. The timedomain comparator, which is based on the edge pursing principle, consists of delay cells, two NAND gates, two D-flip-flop register-based phase detectors and a counter. The digital characteristic of the comparator makes the design more flexible, and the comparator can achieve noise and power optimization automatically by simply adjusting the delay cell number. An energy efficient digital-to-analog converter (DAC) control scheme suitable for the skipping window technique is also developed to reduce the switching energy during SAR conversion. Together with the skipping-window technique, the linearity and the power consumption of the SAR ADC are improved. The impact of different window sizes on comparison cycles, DAC switching energy and the overall energy efficiency is analyzed. Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC, as well as the linearity, and the optimized window size for the overall energy efficiency will vary with the DAC switching energy.

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“…In [23], the use of a bidirectional comparator relieves the circuit from the trade-off of power and noise level but the comparator's threshold comparison level is dependent on the input signal which can affect the bandwidth and linearity. In [24], by using the voltage-controlled delay line (VCDL), the authors propose an adaptive time-domain (ATD) comparator that adjusts the noise performance; however, the performance is still restricted to the linearity of the VCDL.…”

Section: Introductionmentioning

confidence: 99%

A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump-Based Comparators in 28-nm CMOS

Esmailiyan

Schembari

Staszewski

2020

IEEE Trans. Circuits Syst. I

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Dickson charge-pump (CP) is proposed here to realize a voltage-to-time converter (VTC) within an array of time-domain comparators of a 54-level time-mode subthreshold flash ADC operating at 0.36 V. Two identical CPs in each of the 54 ADC slices convert the input and reference voltages into variable-slope ramp signals fed into comparators for 'flash' quantization. Considering the fact that the comparator's evaluation time gets severely degraded at subthreshold input voltages, the proposed ADC delivers the maximum bandwidth by means of the inherent input voltage boosting by the Dickson CPs. The proposed architecture quantizes the analog input signal into time with CPs and then into digital domain with latches and simple logic, without using any analog-intensive circuits such as amplifiers and current sources, thus yielding a digitally friendly implementation. Measurement results show peak ENOB of 5.04-bit, SNDR of 32.1 dB at the peak, power consumption of 88 µW. The conversion rate of 5 MS/s is the highest among near-and subthreshold ADCs. Index Terms-Flash analog-to-digital converter (ADC), time-based ADC, subthreshold ADC, Dickson charge pump (CP), time quantization, voltage-to-time converter (VTC), wideband subthreshold ADC.

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A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization

Cited by 5 publications

References 10 publications

A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows

A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows

A Time-Domain Comparator Based Skipping-Window SAR ADC

A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump-Based Comparators in 28-nm CMOS

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