We present a 0.2-V open-loop voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) intended for IoT wireless sensor nodes. A resistor-based frequency-tuning scheme helps in mitigating odd-order harmonic distortion induced by the VCO nonlinear transfer characteristic. It also provides a reconfigurable input range, allowing it to exceed the supply by 2.5× (single-ended), and maintaining tolerance against ±10% supply variations. Latch, flip-flops, and logic gates within the frequency-to-digital converter are designed for minimum propagation delays, allowing sampling at 30 MS/s. The ADC is implemented in 28-nm CMOS and achieves a peak SNDR of 68 dB, equivalent to an ENOB of 11, over a 61-kHz bandwidth with a 1-V pp input differential sinewave. It consumes 7 µW, resulting in a state-of-the-art Walden and Schreier FoM of 27.8 fJ/c-s and 167.4 dB, respectively.

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This article introduces a digitally intensive eventdriven quasi-level-crossing (quasi-LC) delta-modulator analogto-digital converter (ADC) with adaptive resolution (AR) for Internet of Things (IoT) wireless networks, in which minimizing the average sampling rate for sparse input signals can significantly reduce the power consumed in data transmission, processing, and storage. The proposed AR quasi-LC delta modulator quantizes the residue voltage signal with a 4-bit asynchronous successive-approximation-register (SAR) sub-ADC, which enables a straightforward implementation of LC and AR algorithms in the digital domain. The proposed modulator achieves data compression by means of a globally signal-dependent average sampling rate and achieves AR through a digital multi-level comparison window that overcomes the tradeoff between the dynamic range and the input bandwidth in the conventional LC ADCs. Engaging the AR algorithm reduces the average sampling rate by a factor of 3 at the edge of the modulator's signal bandwidth. The proposed modulator is fabricated in 28-nm CMOS and achieves a peak SNDR of 53 dB over a signal bandwidth of 1.42 MHz while consuming 205 µW and an active area of 0.0126 mm 2. Index Terms-Adaptive resolution (AR), analog-to-digital converter (ADC), asynchronous successive-approximation-register (SAR) ADC, compressed sensing, event-based signal processing, Internet of Things (IoT), level crossing (LC).

Dickson charge-pump (CP) is proposed here to realize a voltage-to-time converter (VTC) within an array of time-domain comparators of a 54-level time-mode subthreshold flash ADC operating at 0.36 V. Two identical CPs in each of the 54 ADC slices convert the input and reference voltages into variable-slope ramp signals fed into comparators for 'flash' quantization. Considering the fact that the comparator's evaluation time gets severely degraded at subthreshold input voltages, the proposed ADC delivers the maximum bandwidth by means of the inherent input voltage boosting by the Dickson CPs. The proposed architecture quantizes the analog input signal into time with CPs and then into digital domain with latches and simple logic, without using any analog-intensive circuits such as amplifiers and current sources, thus yielding a digitally friendly implementation. Measurement results show peak ENOB of 5.04-bit, SNDR of 32.1 dB at the peak, power consumption of 88 µW. The conversion rate of 5 MS/s is the highest among near-and subthreshold ADCs. Index Terms-Flash analog-to-digital converter (ADC), time-based ADC, subthreshold ADC, Dickson charge pump (CP), time quantization, voltage-to-time converter (VTC), wideband subthreshold ADC.