2018
DOI: 10.1109/lssc.2019.2906777
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A 0.2-V 30-MS/s 11b-ENOB Open-Loop VCO-Based ADC in 28-nm CMOS

Abstract: We present a 0.2-V open-loop voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) intended for IoT wireless sensor nodes. A resistor-based frequency-tuning scheme helps in mitigating odd-order harmonic distortion induced by the VCO nonlinear transfer characteristic. It also provides a reconfigurable input range, allowing it to exceed the supply by 2.5× (single-ended), and maintaining tolerance against ±10% supply variations. Latch, flip-flops, and logic gates within the frequency-to-digi… Show more

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Cited by 27 publications
(39 citation statements)
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“…Consequently, the overall falling edge delay τ d f and the overall rising edge delay τ dr are obtained by the averaging Eqs. (15,16) as well, but this time substituting Eq. (19) and the equivalent expressions for τ dr+ and the negative half cell delays.…”
Section: Differential Delay Cell With Feed-forward Cross-couplingmentioning
confidence: 99%
See 2 more Smart Citations
“…Consequently, the overall falling edge delay τ d f and the overall rising edge delay τ dr are obtained by the averaging Eqs. (15,16) as well, but this time substituting Eq. (19) and the equivalent expressions for τ dr+ and the negative half cell delays.…”
Section: Differential Delay Cell With Feed-forward Cross-couplingmentioning
confidence: 99%
“…(20) and taking into account the balancing effect due to the differential nature, see Eqs. (15,16), a similar noise calculation can be done for the direct cross-coupled VCO delay cell:…”
Section: B Differential Delay Cell With Direct Cross-couplingmentioning
confidence: 99%
See 1 more Smart Citation
“…11(a) (the figure shows the bottom drive version), originally proposed in [48]. Various implementations [10], [48]- [50] have demonstrated up to 11 bits of linearity in a pseudo-differential VCO-based ADC.…”
Section: Circuit Design Aspects For Vco-based Analog-to-digital Converters a Single-ended Inverter-based Ring Oscillatorsmentioning
confidence: 99%
“…The clock's phase is then sampled and differentiated such that the ADC's digital output is ideally proportional to the analog input. Unfortunately, the nonlinearity of the VCO's voltage-to-frequency conversion, which originates from the active devices, will directly affect the ADC's nonlinearity, thus requiring extensive calibration due to PVT variations [3].…”
Section: Introductionmentioning
confidence: 99%