No abstract

Recently an extremely linear voltage-controlled ring-oscillator for use in VCO-ADCs was proposed by Babaie-Fishani and Rombouts. In this current Letter, a circuit-level technique to improve the bandwidth and noise performance of such a linear VCO is proposed. The key element is the modified delay cell, where the traditional cross-coupled inverters are modified into 'feed-forward' coupling inverters that pre-charge the subsequent elements in the ring. The resulting circuit maintains the excellent linearity, but has greatly enhanced bandwidth (up to 3 times higher) and considerably reduced power for the same circuit noise level (up to 2.5 times lower).

We present a compact, versatile Hall readout system with digital output, fully integrated in 180 nm technology. The core of the system is an instrumentation amplifier architecture that provides inherent anti-aliasing filtering, where the anti-aliasing characteristic is locked into a shape that maximally prevents aliasing to low frequencies. The efficiency for blocking out-of-band white noise is comparable to that of a second-order filter, eliminating the need for an explicit anti-aliasing filter before the ADC. Chopping/spinning is applied for up-modulating offset and 1/f noise to just beyond the signal band. A mostly-digital ripple reduction loop (RRL) is added for mitigating offset-related dynamic range limitations. In this, a bilinear integrator is introduced for eliminating the impact of the RRL on the system's DC gain. Moreover, the resolution of the DAC generating the analog offset compensation is reduced significantly, and the effect thereof is eliminated by digital noise cancellation logic. The one-step amplification and the simple, lowresolution DAC for offset compensation both aid in keeping the area footprint low: the analog circuits (including DAC and ADC) only occupy 0.21 mm 2 . Notable performance characteristics are an input-referred noise floor of 55 nT/ √ Hz within a 410 kHz bandwidth, a current consumption of only 5.1 mA, and a 47 dB dynamic range. The amplifier architecture can be easily applied as an analog preconditioning circuit in other sensor readout situations as well.

For the design of ring oscillator-based ADCs, little has been reported on how to optimally co-design the readout scheme and the ring oscillator core towards optimal energy efficiency. This paper describes a methodology to find this optimum for a target SQNR and signal bandwidth, for the case of 1 st -order quantization noise shaping. In short, starting from initial assumptions on the VCO, the readout optimization boils down to finding the best VCO frequency. From this, the number of readout phases, the sampling frequency of the readout and the number of bits in the quantizers are derived. Then, it is explained how to adjust the VCO core toward the corresponding optimal VCO configuration. This is discussed for the case of a current-controlled ring oscillator, indicating the main constraints that define the design space for such a VCO optimization. If the actual VCO configuration is bounded by practical constraints, this approach can be re-iterated where a new readout optimization is performed taking these constraints into account.

No abstract