Methodology for Readout and Ring Oscillator Optimization Toward Energy-Efficient VCO-Based ADCs

Abstract

For the design of ring oscillator-based ADCs, little has been reported on how to optimally co-design the readout scheme and the ring oscillator core towards optimal energy efficiency. This paper describes a methodology to find this optimum for a target SQNR and signal bandwidth, for the case of 1 st -order quantization noise shaping. In short, starting from initial assumptions on the VCO, the readout optimization boils down to finding the best VCO frequency. From this, the number of readout phases, the sampling frequency of the readout and the number of bits in the quantizers are derived. Then, it is explained how to adjust the VCO core toward the corresponding optimal VCO configuration. This is discussed for the case of a current-controlled ring oscillator, indicating the main constraints that define the design space for such a VCO optimization. If the actual VCO configuration is bounded by practical constraints, this approach can be re-iterated where a new readout optimization is performed taking these constraints into account.

Exploring Speed Maximization of Frequency-to-Digital Conversion for Ultra-Low-Voltage VCO-Based ADCs

“…3(c) extends the counter-based structure (integer-count value) to detect the phase transitions in a power-efficient manner (fractional-count value). The power efficiency of this architecture is similar to the XOR-based FDC (with decimation, it actually becomes superior) [24]. However, all of the issues encountered in the counter-based FDC (and their remedies) are inherited here.…”

“…Here, the need for a large OSR dictates the first stages of the digital filter to operate as fast as the speed-maximized phase sampling interface. Moreover, utilizing the multi-phase outputs of the ring-VCO results in a significant portion of the ADC's hardware dedicated to the output summation logic to perform digital recombination of the parallel FDC streams [24]. Aside from the necessary additional power consumption, the combination of high-speed operation and large mismatch-induced delay variability may compromise the functionality of these seemingly trivial digital blocks in deepsubthreshold.…”

“…The class of hardware used for frequency-to-digital conversion seems particularly affected by the deep-subthreshold operation, yet, it has remained relatively unexplored. Frequency-to-digital converters (FDCs) are most known for their use in the voltage-controlled-oscillator (VCO)-based analog-to-digital converter (ADC), where they provide a precise digitization of the frequency-modulated (FM) VCO output [18], [19], [20], [21], [22], [23], [24], [25], [26], [27]. FDCs have also found importance in all-digital phase-lockedloops (ADPLLs) requiring high-speed phase accumulators [28], [29], [30].…”

The Mismatch Performance of Pseudo Digital Ring Oscillators Used in VCO ADCs: PSRR and CMRR

“…Note that in [25], [26], [14], [12], and [13] a similar observation was made for the input-referred 1/ f noise of a ring oscillator. It is important to realize that the number of delay cells, N, also affects the readout performance of the VCO in a VCO-ADC system substantially [27]. We will start our analysis below for the case of ideal voltage control: i.e.…”

A maximally-digital VCO-ADC with inherent mixing input capability

“…VCOs, a number of techniques have been developed [12]- [14] that mitigate VCO non-linearity with small power and area. However, a problem common to many VCO-ADCs is the restriction to first-order noise shaping, especially when the sampling rate is forced by industry standards (like in a MEMS microphone) or limited by technology (like in high speed data converters), [15]. In a first-order VCO-ADC, the oscillator effective frequency f e , defined as the product of the RO rest frequency f 0 times the number of VCO phases M , is proportional to the resolution required [16].…”