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We present a compact, versatile Hall readout system with digital output, fully integrated in 180 nm technology. The core of the system is an instrumentation amplifier architecture that provides inherent anti-aliasing filtering, where the anti-aliasing characteristic is locked into a shape that maximally prevents aliasing to low frequencies. The efficiency for blocking out-of-band white noise is comparable to that of a second-order filter, eliminating the need for an explicit anti-aliasing filter before the ADC. Chopping/spinning is applied for up-modulating offset and 1/f noise to just beyond the signal band. A mostly-digital ripple reduction loop (RRL) is added for mitigating offset-related dynamic range limitations. In this, a bilinear integrator is introduced for eliminating the impact of the RRL on the system's DC gain. Moreover, the resolution of the DAC generating the analog offset compensation is reduced significantly, and the effect thereof is eliminated by digital noise cancellation logic. The one-step amplification and the simple, lowresolution DAC for offset compensation both aid in keeping the area footprint low: the analog circuits (including DAC and ADC) only occupy 0.21 mm 2 . Notable performance characteristics are an input-referred noise floor of 55 nT/ √ Hz within a 410 kHz bandwidth, a current consumption of only 5.1 mA, and a 47 dB dynamic range. The amplifier architecture can be easily applied as an analog preconditioning circuit in other sensor readout situations as well.

In this paper, a Hall plate readout with a randomized four-phase spinning-current scheme is proposed. The goal is to remove the maximum number of offset components, including the offset associated with spike demodulation. The outcome is that only the smallest possible offset remains, corresponding to the residual offset of the Hall plate which cannot be distinguished from the Hall signal. An additional innovation is to operate various offset-reduction loops in spread-spectrum mode, allowing the removal of error components without notching out any in-band signals. The resulting approach delivers a very large notch-free bandwidth while simultaneously reducing the Hall plate residual offset, making it an enabler for high-bandwidth Hall-based current sensors. To demonstrate the proposed techniques, we have realized a mixed-mode experimental circuit, where the analog part is implemented in a custom integrated circuit, and the digital control system in an FPGA is connected to the analog chip. Measurement results feature a Hall readout system with a notch-free bandwidth up to 820 kHz and a 47 μTrms noise floor. The input-referred Hall plate offset, based on statistical measurements on 10 samples from a single wafer, is reduced from 130±22μT to only 23±22μT.

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