A 0.5 V, 420 MSps, 7-bit flash ADC using all-digital time-domain delay interpolation

Lin, James; Mano, Ibuki; Miyahara, Masaya; Matsuzawa, Akira

doi:10.1109/edssc.2012.6482785

Cited by 5 publications

(6 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The delay time of the TB-STAL is less than half that discussed in Ref. [8] and its power consumption is less than that presented in Ref [8]. The offset voltage after the calibration and the noise voltage of the TB-STAL are also sufficiently small for use in a 6-bit flash ADC.…”

Section: Temporarily Boosted Comparatormentioning

confidence: 81%

“…Another conventional comparator, which is shown in Figure 2, overcomes the above mentioned problems [8]. A varactor comprised of metal oxide metal (MOM) capacitors and MOS switches are used to compensate for the offset voltage.…”

Section: Problem With Conventional Low Voltage Comparatorsmentioning

confidence: 99%

“…On the other hand, a flash ADC is tolerant of the speed degradation in the comparator because the comparator is used only once for the conversion [4]- [6]. Therefore, several previous works on low-voltage and high-speed flash ADCs have been conducted [7] [8]. These ADCs run on a 0.5-V supply voltage; however, the sampling frequencies are 600 MHz and 420 MHz, which are insufficient values for the above-mentioned applications.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 0.5-V, 1.2-GS/s, 6-Bit Flash ADC Using Temporarily-Boosted Comparator

Ohhata¹,

Masataro²,

Yamaguchi³

2015

View full text Add to dashboard Cite

A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address this problem. The proposed circuit only boosts the supply voltage in the comparison phase, and therefore, can reduce the delay time while keeping the power overhead to a minimum. Moreover, the body bias control calibration is combined with the temporarily boosted technique. This helps to create a low-power and high-precision comparator. A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique. The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and an FOM of 28 fJ/conv.-step even at a low supply voltage of 0.5 V.

show abstract

Section: Temporarily Boosted Comparatormentioning

confidence: 81%

Section: Problem With Conventional Low Voltage Comparatorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 0.5-V, 1.2-GS/s, 6-Bit Flash ADC Using Temporarily-Boosted Comparator

Ohhata¹,

Masataro²,

Yamaguchi³

2015

View full text Add to dashboard Cite

show abstract

“…In this paper, the research topic of ULV high-speed design for flash ADCs is explored [18], [21]. In Section II, the concept of the FD product proposed in [18] is further elaborated to include second-order effects; thus, this paper provides a more comprehensive explanation of the FD product.…”

Section: Introductionmentioning

confidence: 99%

“…However, the implementation of this technique introduced two additional stages of comparators limiting its power saving potential. To alleviate the power consumption from the added comparators, [20] and [21] implemented an all-digital solution. This virtually halves the power consumption, input capacitance, and chip area compared with the conventional design.…”

Section: Introductionmentioning

confidence: 99%

Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product

Lin

Mano

Miyahara

et al. 2015

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

This paper discusses the ultralow-voltage (ULV) design strategy for high-speed flash analog-to-digital converters (ADCs). A lower supply voltage decreases the energy consumption at the cost of conversion speed. In this paper, a new index, the figure-of-merit (FoM)-delay (FD) product, is introduced to provide a balance between the energy efficiency and conversion speed. As a prototype, a 0.5 V, 420-MS/s, and 7-bit, flash ADC is developed using a 90-nm CMOS technology to demonstrate the validity of ULV operation. To overcome the challenges associated with a reduced supply voltage, a double-tail latched comparator with a variable capacitance calibration technique using metal- oxide-metal capacitors is implemented. An all-digital timedomain delay interpolation technique further enhances the resolution with very little additional power consumption. Using twoway time-interleaving, the prototype ADC achieves an effective number of bits (ENOB) of 5.5 bitswhile operating at 420 MS/s consuming a total power of 4.1 mW. The lowest measured FoM is the 195 fJ/conv.-step during single-channel operation at 210 MS/s, which results in an extremely low FD product of 0.93 pJ × ns/conv.-step. Index Terms-Analog-to-digital converter (ADC), delay interpolation, figure-of-merit (FoM)-delay (FD) product, flash, high speed, ultralow voltage (ULV).

show abstract