Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product

Abstract

This paper discusses the ultralow-voltage (ULV) design strategy for high-speed flash analog-to-digital converters (ADCs). A lower supply voltage decreases the energy consumption at the cost of conversion speed. In this paper, a new index, the figure-of-merit (FoM)-delay (FD) product, is introduced to provide a balance between the energy efficiency and conversion speed. As a prototype, a 0.5 V, 420-MS/s, and 7-bit, flash ADC is developed using a 90-nm CMOS technology to demonstrate the validity of ULV operation. To overcome the challenges associated with a reduced supply voltage, a double-tail latched comparator with a variable capacitance calibration technique using metal- oxide-metal capacitors is implemented. An all-digital timedomain delay interpolation technique further enhances the resolution with very little additional power consumption. Using twoway time-interleaving, the prototype ADC achieves an effective number of bits (ENOB) of 5.5 bitswhile operating at 420 MS/s consuming a total power of 4.1 mW. The lowest measured FoM is the 195 fJ/conv.-step during single-channel operation at 210 MS/s, which results in an extremely low FD product of 0.93 pJ × ns/conv.-step. Index Terms-Analog-to-digital converter (ADC), delay interpolation, figure-of-merit (FoM)-delay (FD) product, flash, high speed, ultralow voltage (ULV).

Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

“…Some of them are high power consumption and large chip area. Especially, due to increasing resolution of fully parallel A/D Converter, input capacitance of this system, chip area and power consumption become larger [7][8][9][10][11].…”