ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) 2019
DOI: 10.1109/esscirc.2019.8902814
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An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibration and Interpolation in 65 nm CMOS

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Cited by 11 publications
(3 citation statements)
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“…(8) The high level of the COMP+ output passes through the OR gate and generates the next DISCH pulse. (9) The high level at the R node clears the Q output of the RS latch. (10) The low value of Q resets the comparator.…”
Section: Methods Descriptionmentioning
confidence: 99%
See 1 more Smart Citation
“…(8) The high level of the COMP+ output passes through the OR gate and generates the next DISCH pulse. (9) The high level at the R node clears the Q output of the RS latch. (10) The low value of Q resets the comparator.…”
Section: Methods Descriptionmentioning
confidence: 99%
“…As the reference voltage is also required for the active feedback, it is not considered as an additional circuitry introduced by the reset method. To mitigate the comparator offset issue, the time-domain offset calibration method is used [9][10][11]. The discharging current can be regulated by means of the 5 bit current-steering digital-to-analog converter (DAC).…”
Section: Methods Descriptionmentioning
confidence: 99%
“…incoming photons. To handle this problem, a time-domain offset compensation technique was applied [10].…”
Section: Jinst 17 C03027mentioning
confidence: 99%