A 0.5 V Receiver in 90 nm CMOS for 2.4 GHz Applications

Designing analog and RF circuits for ultra-low supply voltages

“…Using an on-chip negative conductance tuning circuit a gain boost of 20dB can be achieved resulting in an overall DC gain of 62dB [23]. Figure 10 illustrates a 0.5V two-stage OTA topology [28] optimized for use in a 90nm CMOS technology where the nominal V T is about 0.3V. Taking advantage of the RSCE by using non-minimum length devices, applying forward body bias on the input devices, and biasing the input transistors towards weak inversion to improve g m efficiency allows to use a standard differential input pair M 1A /M 1B while maintaining the input common mode at 0.25V.…”

“…In this design, the body voltages of all NMOS devices are adjusted together in order to compensate for part of the V T variations over process, temperature and voltage; a similar PMOS body bias circuit is used (not shown). This OTA achieves a DC gain of 45dB, a gain-bandwidth product of 175MHz for a load capacitance of 4pF and a power consumption of 625µW from a 0.5V supply and was used in the design of variable gain amplifiers and continuous-time baseband filters [28]. …”

“…If the V T of the transistors is relatively large, switches can be connected to the level-shifted virtual ground node to obtain sufficient ON conductance. If the switch V T can be kept sufficiently low by sizing for RSCE and by connecting the body to the gate terminal [31], level shifting is not even required (e.g., see [28] for an example in 90nm CMOS).…”

“…As such, standard inductively degenerated low noise amplifier topologies can be scaled to supply voltages as low at 0.5V while maintaining good performance [28] [36]. The design of ultra-low voltage mixers is significantly more challenging.…”

“…Switched-transconductor mixers [37] offer an interesting low-voltage alternative. Using current-source loads with local common-mode feedback and level shifting [36] for low or zero-IF architectures, or using inductive loads [28] for sliding-IF architectures such mixers can be designed to operate down to 0.5V. An important challenge is the design of LO buffers to obtain the rail-to-rail LO signal required to drive this mixer [36].…”