A 0.5-V Sub-10-μW 15.28-mΩ/√Hz Bio-Impedance Sensor IC With Sub-1° Phase Error

Kim, Kwantae; Kim, Jihoon; Gweon, Surin; Kim, Minseo; Yoo, Hoi‐Jun

doi:10.1109/jssc.2020.2991511

Cited by 29 publications

(17 citation statements)

References 37 publications

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“…For the generation of DAC-based sinusoids, direct digital synthesizers (DDSs) are widely used in on-chip EIS systems [35], [36], [39], [47], [48]. Fig.…”

Section: A Dac-based Sinusoidmentioning

confidence: 99%

“…CT filters have been widely adopted in on-chip SSGs [35], [36], [38], [39], [44], [45], [47], [51], [52], [59], [62], [63], [73], [101], [102]. The most simple but fundamental CT filter is passive RC LPFs.…”

Section: A Linearity Enhancement In Ct Domainmentioning

confidence: 99%

“…Alternatively, active g m -C filters have been adopted for decreasing the minimum f SG with small die area [38], [39], [44], [51], [52], [59], [73], [101], [102]. Fig.…”

Section: A Linearity Enhancement In Ct Domainmentioning

confidence: 99%

“…For implantable EIS systems, the power consumption should be low. For example, for ensuring the life time of pacemaker over 10 years, the power consumption of the EIS system is required to be less than 10 μW [39]. To save the power consumption, implantable EIS systems often support one or a few particular frequencies only at low frequency like the one shown in Table I [38].…”

Section: Introductionmentioning

confidence: 99%

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On-Chip Sinusoidal Signal Generators for Electrical Impedance Spectroscopy: Methodological Review

Kweon¹,

Rafi

Cheon

et al. 2022

IEEE Trans. Biomed. Circuits Syst.

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This paper reviews architectures and circuit implementations of on-chip sinusoidal signal generators (SSGs) for electrical impedance spectroscopy (EIS) applications. In recent years, there have been increasing interests in on-chip EIS systems, which measure a target material's impedance spectrum over a frequency range. The on-chip implementation allows EIS systems to have low power and small form factor, enabling various biomedical applications. One of the key building blocks of on-chip EIS systems is on-chip SSG, which determines the frequency range and the analysis precision of the whole EIS system. On-chip SSGs are generally required to have high linearity, wide frequency range, and high power and area efficiency. They are typically composed of three stages in general: waveform generation, linearity enhancement, and current injection. First, a sinusoidal waveform should be generated in SSGs. The generated waveform's frequency should be accurately adjustable over a wide range. The firstly generated waveform may not be perfectly linear, including unwanted harmonics. In the following linearity-enhancement step, these harmonics are attenuated by using filters typically. As the linearity of the waveform is improved, the precision of the EIS system gets ensured. Lastly, the filtered voltage waveform is now converted to a current by a current driver. Then, the current sinusoidal signal is injected into the target impedance. This review discusses the principles, advantages, and disadvantages of various techniques applied to each step in state-of-the-art on-chip SSGs. In addition, state-of-the-art designs are compared and summarized.

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“…For the generation of DAC-based sinusoids, direct digital synthesizers (DDSs) are widely used in on-chip EIS systems [35], [36], [39], [47], [48]. Fig.…”

Section: A Dac-based Sinusoidmentioning

confidence: 99%

Section: A Linearity Enhancement In Ct Domainmentioning

confidence: 99%

“…Alternatively, active g m -C filters have been adopted for decreasing the minimum f SG with small die area [38], [39], [44], [51], [52], [59], [73], [101], [102]. Fig.…”

Section: A Linearity Enhancement In Ct Domainmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

On-Chip Sinusoidal Signal Generators for Electrical Impedance Spectroscopy: Methodological Review

Kweon¹,

Rafi

Cheon

et al. 2022

IEEE Trans. Biomed. Circuits Syst.

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show abstract

“…However, most of them traded off between power and latency. In [3], a 142 nW VAD IC using sequential mixer-based FEx was proposed where the operational principle is similar to that used for bio-impedance sensors [4], [5]. However, this sequential frequency scanning is too undersampled for the KWS and results in a 512 ms latency for VAD.…”

Section: Introductionmentioning

confidence: 99%

A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction

Kim

Gao²,

Graça³

et al. 2022

IEEE J. Solid-State Circuits

Self Cite

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This article presents the first keyword spotting (KWS) IC which uses a ring-oscillator-based time-domain processing technique for its analog feature extractor (FEx). Its extensive usage of time-encoding schemes allows the analog audio signal to be processed in a fully time-domain manner except for the voltage-to-time conversion stage of the analog front-end. Benefiting from fundamental building blocks based on digital logic gates, it offers a better technology scalability compared to conventional voltage-domain designs. Fabricated in a 65 nm CMOS process, the prototyped KWS IC occupies 2.03mm 2 and dissipates 23 µW power consumption including analog FEx and digital neural network classifier. The 16-channel time-domain FEx achieves 54.89 dB dynamic range for 16 ms frame shift size while consuming 9.3 µW. The measurement result verifies that the proposed IC performs a 12-class KWS task on the Google Speech Command Dataset (GSCD) with >86% accuracy and 12.4 ms latency.

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Advancing Electrical Impedance Spectroscopy (EIS): Low-power, High-accuracy, Wide-dynamic-range, and High-throughput Impedance Measurement Circuits and Architectures

Choi,

Cheon,

Kang

et al. 2024

Low-Cost Diagnostics

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This chapter offers an extensive introduction to readout circuit architectures designed to measure impedances across a frequency range in electrical impedance spectroscopy (EIS). The impedance readout circuit, an essential component of on-chip EIS systems, significantly affects key system performances, including precision and speed of measurements, noise, and power consumption. With an increasing demand for implantable, wearable, and portable EIS systems, researchers have been focusing on achieving higher energy efficiency while maintaining high precision and speed in measurements. Additionally, to improve the compactness and ease of use of EIS systems, various systems use two-electrode and dry-electrode setups rather than the conventional four- and wet-electrode configurations. Numerous innovative methods have been developed to provide reliable measurements using two- and dry-electrode interfaces. This chapter discusses advances in impedance-readout architectures and their pros and cons. These approaches are designed to achieve low power consumption, broad frequency and input ranges, high accuracy with low noise, rapid measurement times, and/or high input impedance. The in-depth analyses of each of these improvements for EIS systems will provide insights into the future progress of small-form-factor EIS systems for biomedical and Internet of Things (IoT) applications.

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A 0.5-V Sub-10-μW 15.28-mΩ/√Hz Bio-Impedance Sensor IC With Sub-1° Phase Error

Cited by 29 publications

References 37 publications

On-Chip Sinusoidal Signal Generators for Electrical Impedance Spectroscopy: Methodological Review

On-Chip Sinusoidal Signal Generators for Electrical Impedance Spectroscopy: Methodological Review

A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction

Advancing Electrical Impedance Spectroscopy (EIS): Low-power, High-accuracy, Wide-dynamic-range, and High-throughput Impedance Measurement Circuits and Architectures

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