A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling

Abstract

In energy-efficient processing platforms, such as wearable sensors and implantable medical devices, dynamic voltage and frequency scaling allows optimizing the energy efficiency under various modes of operation. The clock generator used in these platforms should be capable of achieving a faster settling time and has a wider operating voltage range. In this brief, a fast lock-in all-digital phase-locked loop (ADPLL) with two operation modes (0.52/1 V) is presented. The proposed ADPLL can quickly compute the desired digitally controlled oscillator control code with high accuracy. Therefore, the proposed ADPLL can achieve a fast setting time with frequency errors <5% within four clock cycles. The proposed ADPLL is implemented using a standard performance 90-nm CMOS process. The output frequency of the ADPLL ranges from 60 to 600 MHz at 1 V, and from 30 to 120 MHz at 0.52 V. The power consumption of the proposed ADPLL is 0.92 mW at (1 V, 600 MHz), and 37 µW at (0.52 V, 120 MHz).Index Terms-All-digital phase-locked loop (ADPLL), digitally controlled oscillator (DCO), dynamic voltage and frequency scaling (DVFS), fast lock-in, low power. 1063-8210

A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology

“…7 shows the frequency error after 4.5 reference clock cycles with different frequency multiplication factors (N), and the reference clock is a 5 MHz clock. Compared to the ADPLL [10], the proposed ADPLL eliminates the requirement for a high-resolution TDC circuit and reduces the frequency error of the frequency estimation to less than 1%. Table I shows a performance comparison with previously published fast lock-in ADPLLs.…”

“…Fast lock-in ADPLLs [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,18,19,20,21] have been developed and applied in biomedical electronic devices, wireless devices with frequency hopping, spread spectrum clock generators, and implantable medical devices. These applications require reduction in standby power consumption and rapid frequency switching.…”

“…In addition, on-chip variations increase the frequency error after ADPLL locking. A frequency estimation algorithm (FEA)-based ADPLL using only one DCO was proposed in [10]. The embedded-cyclic TDC improved the accuracy of the period ratio computation and achieved fast setting time with small frequency errors in four clock cycles.…”

“…2. [10] with a cyclic TDC, the period ratio (R value) can be estimated as a fixed-point number, but doing so warrants the use of a highresolution TDC. In the proposed ADPLL, we use a simple cyclic counter triggered by the DCO to compute the period ratio (R value); thus, the R value is an integer number.…”

“…3-9 can achieve almost the same performance in frequency estimation with the fixed-point period ratio (R value). Compared to the ADPLL [10] with a cyclic TDC, the proposed ADPLL can eliminate the requirement of a high-resolution TDC circuit and reduce the frequency error in frequency estimation. Fig.…”