A 0.55mW Fractional-N PLL with a DC-DC Powered Class-D VCO Achieving Better than -66dBc Fractional and Reference Spurs for NB-IoT

Kooshkaki, Hossein Rahmanian; Mercier, Patrick P.

doi:10.1109/cicc48029.2020.9075944

Cited by 12 publications

(5 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A class-D VCO can efficiently use the triode region and improve phase noise performance by using the second harmonic to restore the gain [202]. Low-power class-D VCO that has a resistor to lower power requirements and enhance phase noise [203]. The complementary inverse class-D switching process ensures that the voltage and current waveforms don't cross over, which results in high energy efficiency.…”

Section: ) Class-c Lcvcomentioning

confidence: 99%

A Comparative Study of Ring VCO and LC-VCO: Design, Performance Analysis, and Future Trends

Sivaraaj,

Majeed

2023

IEEE Access

View full text Add to dashboard Cite

Voltage-controlled Oscillator (VCO) is a prominent part that has been used to generate a stable frequency for the high-frequency transceiver system. This survey encompasses a comparative analysis of two commonly used VCO architectures: the Ring VCO and LC-VCO. The Ring VCO has been constructed with the collection of ring delay cells. Moreover, the LC-VCO utilizes inductors, capacitors, fine-tuning circuits, coarse-tuning circuits to generate frequency. Furthermore, this study investigates an in-depth exploration of VCO structures, operational principles, advantages, limitations, and performance metrics. In addition, it evaluates performance parameters, including operating frequency range, phase noise, figure of merit, and tuning techniques. This research suggests that based on the application and its requirements, the VCO performance parameters need to be varied. This survey employs diverse types of VCO, and its design methods. Implications for future research and study of VCO design and integration are discussed.

show abstract

Section: ) Class-c Lcvcomentioning

confidence: 99%

A Comparative Study of Ring VCO and LC-VCO: Design, Performance Analysis, and Future Trends

Sivaraaj,

Majeed

2023

IEEE Access

View full text Add to dashboard Cite

show abstract

“…In addition, this block contains a DC-DC converter to minimize power consumption. In this study, to reduce the power overhead of DC-DC conversion, a switched-capacitor converter is used to generate the VCO supply voltage [15]. It has high efficiency by design so that it can provide a low supply for the VCO without adding large spurs through multiphase interleaving and careful switching frequency selection.…”

Section: Constant Amplitude Control Class-c Vco With Dc-dc Convertermentioning

confidence: 99%

“…By employing 4-phase interleaving, the switched-capacitor output ripple is reduced. To avoid this spur, the switched-capacitor DC-DC converter is designed to operate at the reference frequency of the PLL, hiding the DC-DC spur below the reference spur or using a method to minimize noise by connecting an LPF (Low Pass Filter) or LDO (Low Drop Out) [15]. In case of the pros and cons, if the DC-DC converter spur is hidden in the PLL reference clock spur, a high switching frequency of the DC-DC converter is required, which is not suitable for RF WPT.…”

Section: Constant Amplitude Control Class-c Vco With Dc-dc Convertermentioning

confidence: 99%

Low Phase-Noise, 2.4 and 5.8 GHz Dual-Band Frequency Synthesizer with Class-C VCO and Bias-Controlled Charge Pump for RF Wireless Charging System in 180 nm CMOS Process

Kim

Hejazi

et al. 2022

Electronics

View full text Add to dashboard Cite

This paper presents an integer-N phase-locked loop (PLL) for an RF wireless charging system. To improve the phase-noise characteristics under low power, a constant amplitude control class-C voltage-controlled oscillator (VCO) with a DC-DC converter, and a bias-controlled charge pump with a feedback loop are proposed. The frequency range of the VCO is 4.5–6.1 GHz, the target frequency of the proposed PLL is 2.4 and 5.8 GHz in the industry–science–medical band. It is designed with a same phase margin and bandwidth using one loop filter. The proposed PLL consumes less than 8 mW from a 1.8 V power supply with a settling time of fewer than 20 μs and an area of 1200 μm × 800 μm in the 180 nm CMOS process. For a carrier frequency offset of 1 MHz, the measured phase noise is −118.5 dBc/Hz at 2.4 GHz and −116.6 dBc/Hz at 5.8 GHz. Its FoM including the phase noise is −197 dB at 2.4 GHz and −202.8 GHz at 5.8 GHz, outperforming other PLLs designed in the 180 nm CMOS process.

show abstract

“…If an attempt is made to implement this system with a coherent receiver, a phase-lock loop (PLL) is needed to achieve phase and frequency synchronization. However, it is shown in [18] that the minimum power consumption of a well-designed PLL is on the order of 0.55mW, i.e., the PLL alone consumes more than half of the total power-consumption budget. Thus, in [16], power-hungry elements, such as matched filters, were replaced with twopole BPFs, soft-decision iterative decoders were replaced by hard-decision decoders, etc.…”

Section: Introductionmentioning

confidence: 99%

On the Use of FFH-MFSK for Ultra-Low Power Communications in a Jamming Environment

Xiang

Milstein

2023

IEEE Access

View full text Add to dashboard Cite

We are interested in a communication system that operates in the presence of an intelligent jammer, under stringent power constraints, but with flexible bandwidth constraints. We optimize some of the key elements in the transceiver design for low power consumption, and thus high complexity components of the system, such as matched filters (MF), forward error correction (FEC) that employs iterative decoders, coherent demodulators, and bandwidth-efficient modulation formats, are not feasible for this research. Rather, our system is designed using M -ary frequency shift keying (MFSK) with non-coherent detection and fast frequency hopping (FFH), optimized two-pole bandpass filters (BPF), and Reed-Solomon (RS) codes with hard-decision decoding. Among other things, we show that by properly optimizing the key parameters of the BPFs and RS codes, we can design the system to be significantly less complex than the MF system with a performance loss of less than 1.4 dB for most scenarios that we considered. Further, the 2-pole BPF system can actually outperform the corresponding MF system by up to 2.4 dB in the presence of multi-tone jamming.INDEX TERMS M -ary FSK, multipath fading, ultra-low power-consumption, non-coherent detection, low-complexity filtering, fast frequency-hopping, partial-band noise jamming, multi-tone jamming, Reed-Solomon codes.

show abstract

A 0.55mW Fractional-N PLL with a DC-DC Powered Class-D VCO Achieving Better than -66dBc Fractional and Reference Spurs for NB-IoT

Cited by 12 publications

References 6 publications

A Comparative Study of Ring VCO and LC-VCO: Design, Performance Analysis, and Future Trends

A Comparative Study of Ring VCO and LC-VCO: Design, Performance Analysis, and Future Trends

Low Phase-Noise, 2.4 and 5.8 GHz Dual-Band Frequency Synthesizer with Class-C VCO and Bias-Controlled Charge Pump for RF Wireless Charging System in 180 nm CMOS Process

On the Use of FFH-MFSK for Ultra-Low Power Communications in a Jamming Environment

Contact Info

Product

Resources

About