A 0.7&amp;#x2013;1.15GHz complementary common-gate LNA in 0.18&amp;#x03BC;m SOI CMOS with &amp;#x002B;15dBm IIP3 and &amp;#x003E;1kV HBM ESD protection

Liempd, Barend van; Ariumi, Saneaki; Martens, Ewout; Chen, Shih-Hung; Wambacq, Piet; Craninckx, Jan

doi:10.1109/esscirc.2015.7313854

Cited by 4 publications

(1 citation statement)

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“…An important limitation of the EB duplexer is that it does not provide filtering, in the TX-or the RX path. Therefore, even with very linear LNA implementations in SOI CMOS [20], [21], some kind of pass-band filtering could still be required within the FEM. Tunable RF band-pass filters could be implemented on-chip by N-path techniques [22], or offchip with tuned SAW resonators [23].…”

Section: Introductionmentioning

confidence: 99%

A +70-dBm IIP3 Electrical-Balance Duplexer for Highly Integrated Tunable Front-Ends

Liempd

Hershberg

Ariumi

et al. 2016

IEEE Trans. Microwave Theory Techn.

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An electrical-balance duplexer achieving state-ofthe-art linearity and insertion loss performance is presented, enabled by partially depleted RF silicon-on-insulator (SOI) CMOS technology. A single-ended configuration avoids the common-mode isolation problem suffered by topologies with a differential low-noise amplifier (LNA). Highly-linear switched capacitors allow for impedance balancing to antennas with <1.5:1 voltage standing wave ratio (VSWR) from 1.9 to 2.2 GHz. +70 dBm input-referred 3 rd -order intercept point (IIP3) is achieved under high transmitter (TX) power (+30.5 dBm max.). TX insertion loss is <3.7 dB and receiver insertion loss is <3.9 dB.

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Section: Introductionmentioning

confidence: 99%