A 0.75V CMOS Low-Noise Amplifier for Ultra Wide-Band Wireless Receiver

Wu, Hui-I; Hsiung, Zi Hao; Jou, Christina F.

doi:10.2529/piers060907041726

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2008

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“…At the same time, improvements in materials technology have allowed integration of more and more devices on the same chip, resulting in increased area. According to theory of scaling [3][4][5][6], the smaller dimensions of an MOS transistor should enhance its speed. The cause of gate delay increase is that drain current decreases at low supply voltages.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Capacitance Across Interconnects of Low-K Dielectric Used in a Deep Sub-Micron Cmos Technology

Avinash¹,

Joshi²,

Mahajan³

2008

PIER Letters

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Abstract-The paper presents the detailed analysis of the interconnect capacitance, crosstalk time and peak crosstalk voltage. The dependency of the couple capacitance and fringe capacitance on the interconnect layer dimensions affects significantly to the interconnect capacitance. The peak crosstalk time obtained to be 13 femtoseconds for 9.6 femtoseconds of propagation delay, while the maximum crosstalk voltage obtained to be 178 mV.

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Section: Introductionmentioning

confidence: 99%