A 0.7V 20fJ/bit inductive-coupling data link with dual-coil transmission scheme

Miura, Noriyuki; Shidei, Tsunaaki; Yang, Yuan; Kawai, S.; Takatsu, Keita; Kiyota, Yuji; Asano, Yuichi; Kuroda, Tadahiro

doi:10.1109/vlsic.2010.5560299

Cited by 10 publications

(8 citation statements)

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“…To overcome these challenges, PWC is being investigated as a wireless 3D integration technology [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32] as described in Sec. I.…”

Section: D Chip Stacking With Pwc Technology a Wired Connection And Pwcmentioning

confidence: 99%

“…Contrast to the capacitive coupling, since the magnetic field is not be attenuated by the silicon substrate, multiple-chip stacking is possible with the inductive coupling. As a result, inductive coupling has been widely investigated as an PWC technology for 3D integration [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32].…”

Section: D Chip Stacking With Pwc Technology a Wired Connection And Pwcmentioning

confidence: 99%

“…Furthermore, the couplers can be formed in existing metal layers without requiring special processing steps, resulting in low manufacturing cost and high reliability. While a lot of initial research was focused on capacitive coupling communication technology for 2.5 and 3D integration [2], [3], inductive coupling technology was later developed to overcome challenges faced by capacitive coupling and to enable more chips to be integrated with higher stacking density [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32].…”

Section: Introductionmentioning

confidence: 99%

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Proximity Wireless Communication Technologies: An Overview and Design Guidelines

Kosuge

Kuroda

2022

IEEE Trans. Circuits Syst. I

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This paper presents an overview of proximity wireless communication (PWC) technologies, their principles, design guidelines and practical applications. In particular, two different applications of PWC are reviewed. One is PWC between stacked chips. Both communication distance and coupler size are several tens of microns. Area and energy efficient design techniques are introduced. Another is PWC between module boards. Both communication distance and coupler size are several millimeters. Energy and area efficient practical designs are introduced for mobile and industrial machinery applications.

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Section: D Chip Stacking With Pwc Technology a Wired Connection And Pwcmentioning

confidence: 99%

Section: D Chip Stacking With Pwc Technology a Wired Connection And Pwcmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Proximity Wireless Communication Technologies: An Overview and Design Guidelines

Kosuge

Kuroda

2022

IEEE Trans. Circuits Syst. I

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“…Pulse-based inductive-coupling techniques [1][2][3][4][5] attract much attention for the high-speed proximity communications. If the power consumption of the transceiver is reduced enough by lowering the power supply voltage, the data rate can be increased by arranging many inductor channels in parallel.…”

Section: Introductionmentioning

confidence: 99%

A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS

Matsubara

Hayashi²,

Johari

et al. 2012

2012 IEEE Radio and Wireless Symposium

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This paper presents a pulse-based inductivecoupling transceiver with adaptive pulse width controller for high-speed wireless proximity communication. Adaptive pulse width controller uses 20 phase clocks generated by a multi-phase digitally-controlled-array-oscillator and prevents the pulse width fluctuation under PVT variation at ultra-low power supply voltage. Pulse generation and its width detection are carried out by the identical multi-phase oscillator, which reduces the circuit area. The test chip implemented in 65nm-CMOS has achieved data rate of 850Mb/s/ch at 0.7V supply voltage and power consumption of 4.1mW.Index Terms -inductive-coupling, ultra-low voltage, pulse width controller, high speed interface, proximity communication.

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“…Since power and some signals are connected using wire bonding, the memory chip and the BB are mounted face-up on the AP and the memory chip, respectively. Thickness of each chip is assumed to be 80um, which is a little thicker than [4,7,8], because it can be considered more practical value for mass production. The inductive-coupling link shown on the left in figure 2 is used for AP-memory, AP-BB, BB-memory communication, that is, three-die communication.…”

mentioning

confidence: 99%

A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors

Shimazaki

Miura

Kuroda

2012

2012 IEEE COOL Chips XV

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I. INTRODUCTIONRecently, mobile internet devices such as a smart phone or a tablet PC are getting popular. All of them require high speed internet connection and various kinds of applications such as a mobile digital TV, two-dimensional / three-dimensional graphics, a video recording, a high resolution camera and so on [1]. Figure 1 shows a simplified block diagram of a high performance mobile phone system. It consists of four major components such as an RF IC, a baseband processor (BB), an application processor (AP) and a memory chip. A baseband processor is an LSI that processes communication functions such like LTE or W-CDMA. An application processor executes operation system and various applications. In this system, bandwidth between AP and BB, or AP and memory needs to be wide enough to realize many wireless applications. Since battery life is always a concern in a mobile system, a lot of efforts have been made to reduce power consumption of a mobile phone system [1]. In order to improve bandwidth and energy efficiency of inter-chip communication, an inductive-coupling link between a processor chip and a memory chip has been proposed [2,3]. Power consumption in [2] is very small and performance is high enough, however, the occupied area is very large, which is not acceptable from a commercial point of view. For area saving, a burst-mode inductive-coupling link has been proposed [4]. Although the burst-mode link can significantly reduce the area, it consumes more transmission power than [2] because it is based on an asynchronous circuit instead of a synchronous one. For substantial area reduction of an inductor, XY coil technique has been proposed [5]. Orthogonal edges of the coil are drawn by using two different metal layers, which enables EDA tools to utilize an area above/below the coil for automated place-and-route (PnR). Multiple-die stacking using an inductive-coupling link has been proposed for some applications to improve performance and energy efficiency at the same time [3,5]. A purpose of this paper is to propose a through-chip interface that consumes small power with less area especially for a mobile phone system and to discuss design methodology for a practical chip design. Figure 2 shows a part of a proposed mobile phone system and its three-dimensional system integration overview. An application processor (AP), a memory chip and a baseband processor (BB) are tightly connected by inductive-coupling links and stacked in a package. In this proposal, the AP is mounted face-down on a package substrate for rich power delivery. Since power and some signals are connected using wire bonding, the memory chip and the BB are mounted face-up on the AP and the memory chip, respectively. Thickness of each chip is assumed to be 80um, which is a little thicker than [4,7,8], because it can be considered more practical value for mass production. The inductive-coupling link shown on the left in figure 2 is used for AP-memory, AP-BB, BB-memory communication, that is, three-die communication. II. HIGH PERFORMANCE AN...

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A 0.7V 20fJ/bit inductive-coupling data link with dual-coil transmission scheme

Cited by 10 publications

References 0 publications

Proximity Wireless Communication Technologies: An Overview and Design Guidelines

Proximity Wireless Communication Technologies: An Overview and Design Guidelines

A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS

A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors

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