A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme

Kuroda, T.; Fujita, T.; Mita, S.; Nagamatu, T.; Yoshioka, S.; Sano, F.; Norishima, M.; Murota, M.; Kako, M.; Kinugawa, M.; Kakumu, M.; Sakurai, T.

doi:10.1109/isscc.1996.488555

Cited by 58 publications

(54 citation statements)

References 2 publications

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“…1 Gate leakage current is different for different types of gates, and we use inverter and 2-input nand gate to reflect gate-wise variation. 2 Only nMOSFETs effectively contribute to input gate leakage current. Thus, if we consider total width of only input nMOSFETs, the percentage goes down (e.g.…”

Section: B Impact Of Input Gate Leakage Currentmentioning

confidence: 99%

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Analysis and optimization of gate leakage current of power gating circuits

Kim

Shin

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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Abstract-Power gating is widely accepted as an efficient way to suppress subthreshold leakage current. Yet, it suffers from gate leakage current, which grows very fast with scaling down of gate oxide. We try to understand the sources of leakage current in power gating circuits and show that input MOSFETs play a crucial role in determining total gate leakage current. It is also shown that the choice of a current switch in terms of polarity, threshold voltage, and size has a significant impact on total leakage current. From the observation of the importance of input MOSFETs, we propose the power optimization of power gating circuits through input control.

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Section: B Impact Of Input Gate Leakage Currentmentioning

confidence: 99%

“…Many circuit level approaches have been proposed including dual threshold CMOS [1], variable threshold CMOS [2], input vector control [3], power gating [4], and so on. Power gating is shown to be especially efficient and conceived as a main circuit technique by many semiconductor companies [5], [6].…”

Section: Introductionmentioning

confidence: 99%

Analysis and optimization of gate leakage current of power gating circuits

Kim

Shin

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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“…Threshold voltage is lowered when a circuit is active and elevated when idle. This can be accomplished by substrate biasing [7], [6] or with dual gate silicon-on-insulator (SOI) technologies [11], [3].…”

Section: Introductionmentioning

confidence: 99%

Leakage control with efficient use of transistor stacks in single threshold CMOS

Johnson

Somasekhar

Roy

1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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“…Although conventional schemes control the substrate bias so that leakage current becomes constant [1] or V dd = 3V th [2], the proposed scheme controls the bias so that the delay in the circuit stays constant. As a result, the distributions of device speeds are squeezed under fast-operation conditions.…”

Section: Introductionmentioning

confidence: 99%