A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS

Runge, Marcel; Schmock, Dario; Kaiser, Tobias; Gerfers, Friedel

doi:10.1109/cicc51472.2021.9431576

Cited by 4 publications

(1 citation statement)

References 5 publications

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“…Figure 2b shows the V TH controllability, by applying voltages up to 3 V to the body of the nMOS (-3 V for the pMOS) altering the threshold voltage by 83 mV/V. This benefit is used for dynamic as well as static body-biasing as reported in [6]- [8].…”

Section: Nm Cmos Soi Technologymentioning

confidence: 99%

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

Wittenhagen

Artz

Scholz

et al. 2022

IEEE Open J. Solid-State Circuits Soc.

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In this article, a 3 GS/s Time-Interleaved (TI) RF Track-and-Hold (TaH) amplifier designed in a 22 nm SOI technology is presented. The TaH amplifier is designed to drive an ADC, which can be either two pipeline-ADCs or two rows of SAR-ADCs. Both TI TaH are driven by a single RF-matched wide-band bulk-controlled Front-End (FE) buffer. The measured TaH amplifier has a SFDR beyond 70 dBc up to 2.5 GHz and remains above 67 dBc till 3 GHz enabling sub-sampling. An overall system bandwidth of 4.5 GHz is achieved with a SNR above 55 dBFS. The ultra-low-jitter clock regeneration has only 45 fs rms jitter not limiting the SNR up to 3 GHz. Two-tone and multi-tone measurements reveal a third intermodulation and inter-band non-linearity with >72 dBFS and >82 dBFS respectively. Off-chip calibration of offset/gain mismatch and time-skew between both TaH-lanes reduce interleaving spurs >75 dBFS utilizing a 37-tap fractional delay FIR filter. The efficient body-bias control of the technology is used to dynamically body-bias the TaH sample-switch increasing bandwidth by 10% improving settling performance while at the same time the leakage decreases. Static body-biasing is also applied to the common-mode-feedback by using the bulk as an control node. The TaH amplifier including the clock generation consumes only 178 mW from a triple 2 V/0.9 V/-0.8 V supply.

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Section: Nm Cmos Soi Technologymentioning

confidence: 99%

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

Wittenhagen

Artz

Scholz

et al. 2022

IEEE Open J. Solid-State Circuits Soc.

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A 3^rd Order CT-ΣΔ Modulator with a Hybrid Loop Filter Employing Passive and Continuous-Time Delay Based Integrators

Xiong

Zhao

Liu

et al. 2022

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

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A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With −101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction

Bolatkale

Rutten

Brekelmans

et al. 2022

IEEE J. Solid-State Circuits

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A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS

Cited by 4 publications

References 5 publications

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

A 3^rd Order CT-ΣΔ Modulator with a Hybrid Loop Filter Employing Passive and Continuous-Time Delay Based Integrators

A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With −101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction

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A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS

Cited by 4 publications

References 5 publications

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

A 3rd Order CT-ΣΔ Modulator with a Hybrid Loop Filter Employing Passive and Continuous-Time Delay Based Integrators

A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With −101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction

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Product

Resources

About

A 3^rd Order CT-ΣΔ Modulator with a Hybrid Loop Filter Employing Passive and Continuous-Time Delay Based Integrators