A 1.0 V, 5.4 pJ/bit GFSK Demodulator Based on an Injection Locked Ring Oscillator for Low-IF Receivers

Abstract

This paper presents an ultra-low power, low cost demodulator for gaussian frequency shift keying (GFSK) receivers that use low intermediate frequencies (IF). The demodulator employs a direct IF to digital data conversion scheme by using an injection-locked ring oscillator (ILRO) with a 1-bit flip-flop. It consumes 2.7 μW from a 1.0 V supply at a data rate of 500 kbps achieving an energy efficiency of 5.4 pJ/bit which is 30 times better than that of the recently presented works. The demodulator also achieves 17.5 dB SNR at 0.1 % BER while operating at the same date rate. The demodulator is implemented in a 0.18 μm standard CMOS process and occupies an active area of 0.012 mm 2. INDEX TERMS Demodulator, GFSK, low power, injection locked ring oscillator, low-IF, CMOS.

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“…The improved demodulator structure is shown in Figure 8. In Figure 9, the RF signal RFIN received by the antenna passes through the voltage doubling rectifier circuit composed of MR1, MR2, MR3, MR4 and C1, C2, C3 to obtain the amplified positive half cycle signal [49]- [50]. Then, the signal recovers the envelope of the data signal through the envelope detector composed of MR4,CD1, and RD1 connected by diodes.…”