A 1.02-<i>μ</i>W STT-MRAM-Based DNN ECG Arrhythmia Monitoring SoC With Leakage-Based Delay MAC Unit

Lee, Kyoung-Rog; Kim, Jihoon; Kim, Changhyeon; Han, Donghyeon; Lee, Juhyoung; Lee, Jinsu; Jeong, Hongsik; Yoo, Hoi‐Jun

doi:10.1109/lssc.2020.3024622

Cited by 17 publications

(1 citation statement)

References 8 publications

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“…They focus on classifying healthy or arrhythmic beats and use aggressive analog filtering to emphasize peaks. Reference [5] detects arrhythmias using digital neural networks. Some others present ECG analog front-ends (AFE) without assessing distortion [6], [7].…”

Section: Introductionmentioning

confidence: 99%

Design of an ECG front-end considering ST segment distortion

Guénégo

Lelandais-Perrault

Avignon-Meseldzija

et al. 2023

2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)

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ECG ST segment should be monitored for myocardial ischemia diagnosis. But this information needs a very accurate ECG acquisition. This paper presents the design of a chopper amplifier filtering the baseline wander and minimizing the added electronic noise with an acceptable ST segment distortion. A method is proposed to estimate the ST segment distortion and compare it to the International Electrotechnical Commission (IEC) standards. The design is achieved using XFAB 180nm technology and validated at transistor-level simulation for typical and worst cases.

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Section: Introductionmentioning

confidence: 99%

Design of an ECG front-end considering ST segment distortion

Guénégo

Lelandais-Perrault

Avignon-Meseldzija

et al. 2023

2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)

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Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Chang

Zhang

et al. 2021

Sci. China Inf. Sci.

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An artificial intelligence (AI) processor is a promising solution for energy-efficient data processing, including health monitoring and image/voice recognition. However, data movements between compute part and memory induce memory wall and power wall challenges to the conventional computing architecture. Recently, the memory-centric architecture has been revised to solve the data movement issue, where the memory is equipped with the compute-capable memory technique, namely, computing-in-memory (CIM). In this paper, we analyze the requirement of AI algorithms on the data movement and low power requirement of AI processors. In addition, we introduce the story of CIM and implementation methodologies of CIM architecture. Furthermore, we present several novel solutions beyond traditional analog-digital mixed static random-access memory (SRAM)-based CIM architecture. Finally, recent CIM tape-out studies are listed and discussed.

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Explainable ECG Beat Classification On The Edge for Smart, Trustworthy and Low-Power Wearables

Bhat,

Raychowdhury

2023

2023 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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A 1.02-μW STT-MRAM-Based DNN ECG Arrhythmia Monitoring SoC With Leakage-Based Delay MAC Unit

Cited by 17 publications

References 8 publications

Design of an ECG front-end considering ST segment distortion

Design of an ECG front-end considering ST segment distortion

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Explainable ECG Beat Classification On The Edge for Smart, Trustworthy and Low-Power Wearables

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