A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs

Yamamoto, Kentaro; Carusone, Anthony Chan

doi:10.1109/jssc.2012.2196732

Cited by 34 publications

(13 citation statements)

References 13 publications

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“…The design becomes extremely difficult if the signal bandwidth increases further. For SC DSM, the MASH architecture is implemented for most high-bandwidth applications [2][3][4][5][6]. The elimination of the active adder reduces the power dissipation in the first stage.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…Therefore, several types of architectures are available for a wide bandwidth DSM implementation by implementing the concepts of high order and multi-bit. MASH is now gaining popularity, and recently published papers for high-bandwidth applications have mostly applied MASH architecture [2][3][4][5][6]. MASH avoids the high OSR and loop order by cascading several inherently stable first-and second-order stages.…”

Section: Introductionmentioning

confidence: 99%

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A 10-MHz multi-bit MASH delta–sigma modulator with analog summing interstage

Wang

Jung

Roh

2015

Analog Integr Circ Sig Process

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This paper presents an improved 4-bit twostage multi-stage noise shaping (MASH) delta-sigma modulator (DSM). The two-stage MASH DSM utilizes the second-order chain of cascade of integrators with feedforward (CIFF) and the cascade of integrators with distributed feedback (CIFB) architectures for the first and second stages, respectively. The 4-bit CIFF requires an active adder, which is conventionally implemented with a highbandwidth high-swing amplifier. In the proposed DSM, the active adder is eliminated and the adder-less integrator is applied in the first stage of the MASH DSM. The first stage quantization noise, which is fed to the second stage, is conventionally extracted from the analog input and digital output of the quantizer in the first stage. The number of quantizer digital output paths increases exponentially with the quantization bit number. A large number of DAC feedback paths in the interstage is avoided by proposing a new interstage topology based on analog summing to derive the first stage quantization noise in the analog domain. The prototype DSM is fabricated in a 0.11-lm CMOS process. When operating from a 1.2-V supply, the modulator achieves 67.8-dB peak SNDR, while consuming 25 mW, with an OSR of 8 at a 160-MHz sampling frequency.

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Section: Measurement Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 10-MHz multi-bit MASH delta–sigma modulator with analog summing interstage

Wang

Jung

Roh

2015

Analog Integr Circ Sig Process

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“…These integration capacitors are providing a dominant pole for compensating the opamp by pole splitting. The comparator circuit [9] employed in this work is shown in Fig. 6.…”

Section: Proposed Multiplexed Sigma Delta Modulatormentioning

confidence: 99%

A novel multichannel analog-to-time converter based on a multiplexed sigma delta converter

Rezaei

Maghsoudloo

Gosselin

2015

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)

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In this paper, a new sigma delta modulator based on a multiplexed input topology is proposed to decrease power consumption and size in implantable bio-interfacing systems. An opamp sharing technique is employed in order to process several input sequentially. The proposed sigma delta modulator integrates each input separately and stores the integrated value inside a dedicated capacitor. We show that the resulting transfer function of the modulator is equivalent for all channels. The proposed circuit has been implemented in a 180-nm TSMC process. The circuit includes 4 channels and consumes 11.5 μW per channel, provides an ENOB of 7.8 bits, and presents a bandwidth of 10 kHz. The chip area for the proposed design is 150 μm x 135 μm for 4 multiplexed inputs.

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“…In addition, conventional OTAs are not power efficient due to their typical class-A operation [1][2][3][4]. As an alternative, zero-crossing-based integrator (ZCBI) circuits have been proposed (Figure 1a) [5][6][7][8][9][10][11][12][13][14][15][16], where zero-crossing-detectors (ZCD) and current sources are used to control the charge transfer.…”

Section: Introductionmentioning

confidence: 99%

“…The nonlinearity due to signal-dependent t d can be reduced by increasing the time constant, but it comes at the cost of reduced speed of the integrator. The trade-off relationship between speed and accuracy can be alleviated by two-phase charging schemes [5,6,[10][11][12][13][14]. In a two-phase charging scheme, the charge transfer phase is divided into two phases: coarse and fine.…”

Section: Introductionmentioning

confidence: 99%

A Charge-Sharing-Based Two-Phase Charging Scheme for Zero-Crossing-Based Integrator Circuits

Min

Shim

2019

Electronics

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As an effort to improve the energy efficiency of switched-capacitor circuits, zero-crossingbased integrators (ZCBI) that consist of zero-crossing detectors and charging circuits have been proposed. To break the trade-off between accuracy and speed, ZCBI typically employs a two-phase charging scheme that relies on an additional threshold for zero-crossing detection. This paper proposes a simpler realization method of the two-phase charging scheme by means of charge sharing. To demonstrate feasibility of the proposed method, we designed and fabricated a second-order delta-sigma modulator in 180-nm complementary metal-oxide-semiconductor (CMOS) technology. The measurement results show that the modulator exhibits a peak signal-to-noise-and-distortion ratio (SNDR) of 46.3 dB over the bandwidth of 156 kHz with the power consumption of 684 µW. We also designed the same modulator in 65-nm CMOS technology and simulation results imply that the proposed circuit is able to achieve a much better energy efficiency in advanced technology.

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A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs

Cited by 34 publications

References 13 publications

A 10-MHz multi-bit MASH delta–sigma modulator with analog summing interstage

A 10-MHz multi-bit MASH delta–sigma modulator with analog summing interstage

A novel multichannel analog-to-time converter based on a multiplexed sigma delta converter

A Charge-Sharing-Based Two-Phase Charging Scheme for Zero-Crossing-Based Integrator Circuits

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