A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change

Yoshihara, Sachio; Nitta, Yoshikazu; Kikuchi, Masatoshi; Koseki, K.; Ito, Yasushi; Inada, Yuji; Kuramochi, Souichiro; Wakabayashi, Hayato; Okano, Masafumi; Kuriyama, H.; Inutsuka, J.; Tajima, A.; Nakajima, Tasuku; Kudoh, Y.; Koga, F.; Kasagi, Y.; Watanabe, S.; Nomoto, Takuya

doi:10.1109/jssc.2006.884868

Cited by 135 publications

(52 citation statements)

References 6 publications

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“…Therefore, the conversion time of two-step SS-ADC is theoretically 16 times faster than that of the conventional SS-ADC. Two-step SS-ADC is suitable for high speed CIS systems [3][4][5][6][7][8]. Fig.…”

Section: Circuit Descriptionmentioning

confidence: 99%

“…Among many kinds of column parallel ADCs, SingleSlope ADC (SS-ADC) is mostly adopted at each column of CIS due to its small chip area and low power consumption [1][2][3][4][5][6]. However, since the conversion speed of SS-ADC is very slow, the frame rate of CIS is also very low.…”

Section: Introductionmentioning

confidence: 99%

“…Thus it is hard to use SS-ADC at the high speed systems like HDTV and high resolution cameras to request a frame rate of 30 frames/s or more at a high resolution. In order to overcome the disadvantage of SS-ADC, many approaches have been reported [5][6][7][8][9]. Among them, cyclic ADC or Successive Approximation Register(SAR) ADC are well-known technique for the high frame rate CIS.…”

Section: Introductionmentioning

confidence: 99%

“…It has a 320 x 240 QVGA resolution with a 2.25 um x 2.25 um 4-Tr Active Pixel Sensor (APS). In order to increase the minimum layout column pitch, even columns and odd column are divided into two parts of pixel array [6]. And each columns consist of a comparator, sync block, and 5-bit, 6-bit SRAM array for reset signal and pixel signal A/D conversion.…”

Section: Introductionmentioning

confidence: 99%

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Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

Hwang¹,

Song²

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320 x 240) resolution. The fabricated chip size is 5 mm x 3 mm, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

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Section: Circuit Descriptionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

Hwang¹,

Song²

2014

JSTS:Journal of Semiconductor Technology and Science

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show abstract

“…Two other parameters, namely power consumption and area, become particularly important for circuits with high number of ADCs. The representative examples of such systems are CMOS image sensors (CISs) [10,16,19,20,22], especially massively parallel CISs [5,[11][12][13]15,21]. For the latter, A/D conversion is implemented at the pixel level, as illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Low-Energy Analog Comparator for A/D Converters in CMOS Image Sensors

Jendernalik

2017

Circuits Syst Signal Process

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This paper proposes a new solution of an ultra-low-energy analog comparator, dedicated to slope analog-to-digital converters (ADC), particularly suited for CMOS image sensors (CISs) featuring a large number of ADCs. For massively parallel imaging arrays, this number may be as high as tens-hundreds of thousands ADCs. As each ADC includes an analog comparator, the number of these comparators in CIS is always high. Detailed analysis shows that power dissipation of a comparator contributes significantly to a total power consumption of an ADC. Thus, minimization of the comparator energy consumption during the analog-to-digital (A/D) conversion of an image frame is crucial for design of CMOS image sensors. Compared to classical dynamic or continuous-time comparators operating in the slope ADC, under the same bias conditions, the proposed comparator shows a 2-3 orders of magnitude reduction of the power consumption. In addition, the proposed topology shows a simple and compact layout and does not require a power-down mechanism. The circuit has been simulated in detail for a 0.18-μm CMOS technology under two different power supply voltages of 1.8 and 1 V. While implemented in a 12-bit slope ADC of a massively parallel CIS, operating at a speed 1000 fps, the energy required for A/D conversion is 0.5 pJ.

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Solid‐State Image Sensors

Fowler

2015

Handbook of Digital Imaging

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This chapter presents an overview of solid‐state image sensor technology. It starts with a historical review of CCDs and MOS image sensors since the late 1960s. Then, the basic theory of silicon photon detection is presented. Pixel‐level optics is described next, followed by an analysis of photodetector quantum efficiency and modulation transfer function. Then, the various noise sources in solid‐state image sensors are reviewed, followed by a discussion about CCD and CMOS image sensor readout architectures. Finally, various methods for extending the dynamic range of solid‐state image sensors are reviewed.

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A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change

Cited by 135 publications

References 6 publications

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

An Ultra-Low-Energy Analog Comparator for A/D Converters in CMOS Image Sensors

Solid‐State Image Sensors

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