A 1.1-V 270-/spl mu/A mixed-signal hearing aid chip

Gata, D.G.; Sjursen, W.; Hochschild, J.R.; Fattaruso, J.W.; Fang, Lei; Iannelli, G.R.; Jiang, Zhongnong; Branch, C.M.; Holmes, Jim; Skorcz, M.L.; Petilli, Eugene; Chen, S.; Wakeman, G.; Preves, David A.; Severin, W.A.

doi:10.1109/jssc.2002.804328

Cited by 49 publications

(18 citation statements)

References 7 publications

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“…An estimated total power consumption of the earpiece based on 0.18 lm CMOS is given in Table 1. It shows the user will need to change the battery approximately once in a month based on typically 10 h usages per day [15], which is quite comparable with most of the hearing aids in the market.…”

Section: Methodsmentioning

confidence: 99%

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Reverberation canceling wireless aid for hearing impaired

Rana¹,

Tang

Liang³

et al. 2007

Analog Integr Circ Sig Process

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The stringent requirements on size and power consumption constrain the conventional hearing aid devices. Besides providing an economic and user friendly aid, reverberation/echo cancellation is an important requirement. With the technological advancements, wireless hearing aids exploiting the usage of multi-microphones, mixed signals and RF signals processing circuits, digital signal processing units sound promising to overcome existing constraints. A new wireless hearing aid system is proposed in this paper. Unlike the previously reported wireless hearing aid concept, it needs only one way data transfer from body unit to the earpiece. It helps in minimizing power consumption in the earpiece RF-linked with a body unit with DSP based reverberation canceling scheme. For this purpose, a noise cancellation algorithm is developed based on beam-forming technique. The functioning of the whole system comprising an earpiece and a body unit has been ensured using the Advanced Design System TM . The ADS compatible behavioral models were developed in order to enable the system level simulation. A comprehensive noise analysis is carried out and validated.

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Section: Methodsmentioning

confidence: 99%

“…A few attempts have been reported in order to solve the existing design problems [6,[8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27]. The schemes for developing wireless hearing aid systems have been discussed in [11] and [13].…”

Section: Introductionmentioning

confidence: 99%

Reverberation canceling wireless aid for hearing impaired

Rana¹,

Tang

Liang³

et al. 2007

Analog Integr Circ Sig Process

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show abstract

“…Prior works on AGCs have mainly focused on either digital or analog approach [1][2][3][4][5][6][7] for low power implementation. The digital implementation [1] is capable of complex control and offers maximum flexibility.…”

Section: Introductionmentioning

confidence: 99%

“…The digital implementation [1] is capable of complex control and offers maximum flexibility. However, it requires a full-rate and high-precision analog-to-digital conversion to generate digital gain control codes, giving rise to an area overhead.…”

Section: Introductionmentioning

confidence: 99%

Dual-mode gain control for a 1 V CMOS hearing aid device with enhanced accuracy and energy-efficiency

Yang

Liu

et al. 2012

Analog Integr Circ Sig Process

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A dual-mode gain control (DMGC) technique is presented for accurate and energy-efficient pre-amplification in the front-end system of a hearing aid chip. Compared with the conventional automatic gain control (AGC) approach, the DMGC approach is characterized by an amplification switching mechanism between the prolinearity discrete gain setting mode and the energy-efficient AGC mode. Thus, the total harmonic distortion (THD) should be significantly improved without incurring any degradation concerning other performances parameters (e.g. gain, noise and power consumption). In order to further enhance the system power efficiency, a self currentadapting (SCA) circuit design technique is proposed. Such SCA circuits are capable of automatically adjusting the bias current in accordance with the sound level. A prototype chip was designed with a 0.13 lm standard CMOS process and tested with 1 V supply voltage. The measurement results show that, for a typical output level of 500 mV p-p , the THD is somewhere below -64 dB, achieving approximately ten times reduction compared to the previously reported works. The power consumption of less than 45 lW has also been obtained. In addition, the typical input referred noise is only 2 lV rms and the maximum gain attainable is up to 39 dB.

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“…Figure 1 shows a block diagram of a typical digital hearing aid system, consisting of five blocks: a preamplifier, a Σ-∆ analog-to-digital converter (ADC), a digital signal processing unit (DSP), a Σ-∆ digital-to-analog converter (DAC), and a receiver driver. Among these individual blocks, an analog front-end that comprises a preamplifier and a Σ-∆ modulator is reported to consume a major part of the total power [2], [3]. Therefore, reducing the power consumption of the analog front-end is attractive to decrease the total system power consumption.…”

Section: Introductionmentioning

confidence: 99%

A 0.9-V 67-μW Analog Front-End using Adaptive-SNR Technique for Digital Hearing Aid

Kim¹,

Lee²,

Song³

et al.

2005 IEEE International Symposium on Circuits and Systems

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Abstract-An analog front-end composed of a preamplifier and a Σ-∆ modulator is proposed and implemented for digital hearing aid chip. Combined gain control (CGC), the technique, which incorporates an automatic gain control (AGC) with an exponential gain control (EGC), is employed to enlarge dynamic range and reduce power consumption. The proposed Σ-∆ modulator exploits adaptive-SNR technique, which generates four different SNRs, thereby achieving low power consumption and optimizing performance. The measured power dissipation of the preamplifier is 35-µW. In case of Σ-∆ modulator, the peak signal-to-noise ratio (SNR) is 86-dB, the average power consumption is 31.4-µW and the variation of SNR is 14-dB. The proposed analog front-end dissipates less than 67-µW from a single 0.9-V supply. The core area of the preamplifier and the Σ-∆ modulator is 0.1-mm 2 and 0.4-mm 2 , respectively, in a 0.25-µm standard CMOS technology.

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A 1.1-V 270-/spl mu/A mixed-signal hearing aid chip

Cited by 49 publications

References 7 publications

Reverberation canceling wireless aid for hearing impaired

Reverberation canceling wireless aid for hearing impaired

Dual-mode gain control for a 1 V CMOS hearing aid device with enhanced accuracy and energy-efficiency

A 0.9-V 67-μW Analog Front-End using Adaptive-SNR Technique for Digital Hearing Aid

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