A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

Garofalo, Angelo; Ottavi, Gianmarco; Mauro, Alfio Di; Conti, Francesco; Tagliavini, Giuseppe; Benini, Luca; Rossi, Davide

doi:10.1109/esscirc53450.2021.9567767

Cited by 10 publications

(5 citation statements)

References 10 publications

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“…Table II summarizes the related works. Although Darkside [23] and Dustin [22] are not vector processors, they also target data-parallel workloads and feature IPU and FPU configurations similar to Yun's, besides being taped out in the same 65-nm technology. However, they use a tightly coupled cluster of scalar processors with independent instruction fetch pipelines.…”

Section: Related Workmentioning

confidence: 99%

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Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS

Perotti

Cavalcante

Ottaviano

et al. 2023

IEEE Trans. Circuits Syst. II

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The nature and heterogeneity of modern workloads force hardware designers to choose between general-purpose processors, which come with superior flexibility, and highlytailored accelerators that boost performance and power efficiency at the cost of extreme specialization. One of the most promising solutions that couple the flexibility of a processor with the performance and efficiency of an accelerator is the vector processor architecture. Since RISC-V has only recently frozen its vector ISA extension, no open-source RISC-V-based vector processor has been fabricated and characterized. This brief presents the Yun SoC, featuring the first implementation of an open-source RISC-V-based vector processor in TSMC's 65-nm technology. Our efficient 4-lane design achieves almost peak theoretical performance on large matrix multiplication problems with an FPU utilization of almost 90%. Yun, with a critical path of 30 FO4 inverter delays, achieves a peak performance of 2.83 GFLOPSDP (at 400 MHz and 1.5 V), a leading-edge area efficiency of 3 GFLOP SP /cycle/MGE, and a peak energy efficiency of 10.8 GFLOPSDP/W (at 100 MHz and 0.85 V). Yun supports integer (64-bit, 32-bit, 16-bit, and 8-bit) and floating-point (64-bit and 32-bit) SIMD data formats, as required by ML and data analytics workloads.

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Section: Related Workmentioning

confidence: 99%

“…All the related chips but [22], [23] are implemented with technologies more advanced than Yun's. For this reason, Table III presents technology-agnostic area and energy efficiency metrics.…”

Section: B Efficiency Comparisonmentioning

confidence: 99%

Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS

Perotti

Cavalcante

Ottaviano

et al. 2023

IEEE Trans. Circuits Syst. II

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“…The results confirm the benefits of the adaptive nature of the proposed RI5CY MAC unit by reducing the area induced by the redundant design used in the RI5CY MAC unit (see Figure 6). We note that another MAC unit with a similar design principle has been developed for RI5CY [70].…”

Section: Energy-efficiency Evaluationmentioning

confidence: 99%

A Bottom-Up Methodology for the Fast Assessment of CNN Mappings on Energy-Efficient Accelerators

Devic

Sassatelli

Gamatié

2023

JLPEA

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The execution of machine learning (ML) algorithms on resource-constrained embedded systems is very challenging in edge computing. To address this issue, ML accelerators are among the most efficient solutions. They are the result of aggressive architecture customization. Finding energy-efficient mappings of ML workloads on accelerators, however, is a very challenging task. In this paper, we propose a design methodology by combining different abstraction levels to quickly address the mapping of convolutional neural networks on ML accelerators. Starting from an open-source core adopting the RISC-V instruction set architecture, we define in RTL a more flexible and powerful multiply-and-accumulate (MAC) unit, compared to the native MAC unit. Our proposal contributes to improving the energy efficiency of the RISC-V cores of PULPino. To effectively evaluate its benefits at system level, while considering CNN execution, we build a corresponding analytical model in the Timeloop/Accelergy simulation and evaluation environment. This enables us to quickly explore CNN mappings on a typical RISC-V system-on-chip model, manufactured under the name of GAP8. The modeling flexibility offered by Timeloop makes it possible to easily evaluate our novel MAC unit in further CNN accelerator architectures such as Eyeriss and DianNao. Overall, the resulting bottom-up methodology assists designers in the efficient implementation of CNNs on ML accelerators by leveraging the accuracy and speed of the combined abstraction levels.

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“…A focus on edge computing has led to the development of specialized multi-core processors that target Internet of Things (IoT) and edge computing applications with tight power constraints [8], [9], [19]. In recent years the availability of multicore MCUs has favored the research in the area of parallelizable algorithms on resource-constrained embedded hardware [20], [21].…”

Section: B Parallel Ultra Low Power Systemsmentioning

confidence: 99%

Parallelizing Optical Flow Estimation on an Ultra-Low Power RISC-V Cluster for Nano-UAV Navigation

Kühne

Magno

Benini

2022

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

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Optical flow estimation is crucial for autonomous navigation and localization of unmanned aerial vehicles (UAV). On micro and nano UAVs, real-time calculation of the optical flow is run on low power and resource-constrained microcontroller units (MCUs). Thus, lightweight algorithms for optical flow have been proposed targeting real-time execution on traditional singlecore MCUs. This paper introduces an efficient parallelization strategy for optical flow computation targeting new-generation multicore low power RISC-V based microcontroller units. Our approach enables higher frame rates at lower clock speeds. It has been implemented and evaluated on the eight-core cluster of a commercial octa-core MCU (GAP8) reaching a parallelization speedup factor of 7.21 allowing for a frame rate of 500 frames per second when running on a 50 MHz clock frequency. The proposed parallel algorithm significantly boosts the camera frame rate on micro unmanned aerial vehicles, which enables higher flight speeds: the maximum flight speed can be doubled, while using less than a third of the clock frequency of previous singlecore implementations.

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A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

Cited by 10 publications

References 10 publications

Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS

Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS

A Bottom-Up Methodology for the Fast Assessment of CNN Mappings on Energy-Efficient Accelerators

Parallelizing Optical Flow Estimation on an Ultra-Low Power RISC-V Cluster for Nano-UAV Navigation

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