A 1–16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator

Nonlinearity Estimation for Compensation of Phase Interpolator in Bang–Bang CDRs

“…This can increase overall loop delay by 5%-15% depending on the loop filter implementation. Whereas [4], TSPI [10] and octagonal PI in [11] are the openloop circuit techniques, the proposed algorithm compensates nonlinearity in closed loop and offers smaller nonlinearity compared with these recent works ( Table I). The closed-loop compensation makes it more immune to choice of process technology and accuracy of MOS device modeling, hence offering easy portability, making it more robust.…”

A 12.5 Gbps clock and data recovery circuit with phase interpolation based digital locked loop

“…The phase interpolator use and signals of two differ- ent phases to synthesize , a new phase between the two phases [10,26]. and come from the same clock source with the same frequency.…”

“…The clock and data recovery (CDR) circuit, critical building block of high speed serial links, is utilised to recover clock and data information from serial data stream in the noisy channel and re-time data signal to the optimal sampling position under low bit error rate (BER) [7,8,9,16,17,18,21]. The conventional phaselocked loop (PLL) based CDR uses a voltage controlled oscillator (VCO) to generate a quadrature clock phase at the data rate of received data sequence, providing a tunable bit rate and convenience of easily integrated for multi-channel serial link application with single frequency tracking loop for reference clock generation avoiding the need for PLLs at each pin reducing the area occupation and power consumption significantly [10,12,22,23,24,25]. The dual-loop phase interpolator (PI) based CDR topology offers the benefits of increased system stability, simple structure, low power, faster acquisition and a lock of jitter peaking compared with a PLL-based CDR that needs a charge pump, an analog filter and VCO to align phase to optimize sampling point [1].…”

Synthesisable glitch‐less phase rotator with conditionally cascading scheme

“…Furthermore, recent researchers have attempted to implement building blocks of CDRs in highly digital‐friendly manners to enable scalable and portable designs [2, 6]. This Letter aids such attempts by providing a solution for synthesising a PR through the automatic design flow.…”

“…A phase rotator (PR) is a circuit component that is widely used in wireline interface applications such as clock and data recoveries (CDRs) [1–5]. CDRs with a forwarded reference clock require a PR after a multiphase clock generator to recover the clock phase of the data sampling point [2, 3, 5], thus the performance of such CDRs varies with that of the PR. PRs are commonly realised in the current‐mode logic (CML) to achieve high linearity and a wide frequency range.…”