A 1/2.7 inch Low-Noise CMOS Image Sensor for Full HD Camcorders

Takahashi, Hideki; Noda, T.; Matsuda, Tadashi; Watanabe, Takashi; Shinohara, M.; Endo, Tadashi; Takimoto, Shinya; Mishima, Ryota; Nishimura, Suzushi; Sakurai, Katsuhito; Yuzurihara, Hiroshi; Inoue, Shunsuke

doi:10.1109/isscc.2007.373518

Cited by 33 publications

(13 citation statements)

References 3 publications

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“…In PWM imagers, pixel signals are readout by density of pulse waves. In the field of high S/N ratio image sensor, the column parallel high gain amplifiers 8) , column parallel analog-digital converter (ADC) 9) , correlated multiple sampling (CMS) technology 10)11) have been reported to be useful for CMOS image sensors.…”

Section: Introductionmentioning

confidence: 99%

[Paper] Floating Capacitor Load Readout Operation for Small, Low Power Consumption and High S/N Ratio CMOS Image Sensors

Wakashima

Kusuhara

Kuroda

et al. 2016

MTA

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Floating capacitor load readout operation for small, low power consumption and high S/N ratio CMOS image sensors and its effects are demonstrated. This readout operation utilizes a floating capacitor load instead of a constant current load as pixel SF driver, and the parasitic capacitor of pixel output vertical signal line as column sample/hold capacitor. Using a 0.18 µm CMOS image sensor technology, two CMOS image sensors were fabricated to verify the effects. The ratio of pixel area to the total effective area is over 92 %. The power consumption for pixel signal readout and pixel readout noise were decreased by over 97 % and 63.8 %, respectively. Also a higher readout gain and a wider linear response range were obtained. Furthermore, it was confirmed that this readout operation becomes more advantageous when decreasing the power supply voltage, which is favorable for ultra-low power sensor network system applications.

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Section: Introductionmentioning

confidence: 99%

[Paper] Floating Capacitor Load Readout Operation for Small, Low Power Consumption and High S/N Ratio CMOS Image Sensors

Wakashima

Kusuhara

Kuroda

et al. 2016

MTA

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“…The most popular way to reduce readout circuit noise is amplifying pixel output using a preamplifier at the foremost stage of readout chain to suppress the noise of following readout chains in high analog gain [1][2][3]. Another approach is multiple sampling which can reduce temporal noise of pixel and readout circuit by sampling the same pixel repeatedly and processing (generally averaging) the sampled data [4,5].…”

mentioning

confidence: 99%

A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple sampling

Lim

Koh

Kim

et al. 2010

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

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The noise performance of CMOS image sensors has improved significantly. The most popular way to reduce readout circuit noise is amplifying pixel output using a preamplifier at the foremost stage of readout chain to suppress the noise of following readout chains in high analog gain [1][2][3]. Another approach is multiple sampling which can reduce temporal noise of pixel and readout circuit by sampling the same pixel repeatedly and processing (generally averaging) the sampled data [4,5]. However, both approaches require additional circuitry in the column readout chain which requires extra silicon area and power consumption. Furthermore, it is hard to implement a decent per-column amplifier in a small pixel pitch sensor, such as 1.4µm pixel, because of narrow layout space. In addition, the second approach requires longer readout time proportional to the number of samples. This paper presents a cost-effective low noise CMOS image sensor readout chain using pseudo-multiple sampling technique.The proposed pseudo-multiple sampling technique is described in Fig. 22.2.1. The basic concept of pseudo-multiple sampling is dividing an A/D conversion into several lower resolution A/D conversions. The quantization step of each lower resolution A/D conversion is M times larger than that of normal A/D conversion where M is the number of pseudo-multiple sampling. Each quantization level of lower resolution A/D conversion has 1 LSB offset of normal A/D conversion to ensure the final result has the same resolution of normal A/D conversion. The final result can be calculated by adding all lower resolution A/D conversion results.The output noise of each lower resolution A/D conversion is approximately 1/M times lower than that of normal A/D conversion, when the input noise standard deviation is higher than the quantization step of lower resolution A/D conversion. Therefore, the output noise of the pseudo-multiple sampling A/D conversion is 1/√M times lower than that of normal A/D conversion, if the noise is completely uncorrelated. It is same as the conventional multiple sampling. However, the noise reduction effect of the pseudo-multiple sampling is limited, although the number of sampling is increased. It is because if the quantization step of lower resolution A/D conversion is higher than the input noise standard deviation, some of lower resolution A/D conversion cannot express the input noise properly. Figure 22.2.2 is the noise reduction simulation result of the conventional multiple sampling and the pseudo-multiple sampling using an ideal A/D converter with input noise applied. The noise is assumed white Gaussian having standard deviation of σ in in normal A/D conversion LSB unit. The simulation result shows the noise reduction performance of the pseudo-multiple sampling is almost same as that of the conventional multiple sampling up to M=σ in , and the output noise is saturated to 0.75×√σ in when M is higher than 4σ in .The pseudo-multiple sampling can be implemented using a conventional single slope ADC structure by altering o...

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“…The sensor is scaled down to get a higher resolution due to higher pixel count. Several approaches such as a Cu process to reduce the pixel height and inner micro-lenses to gather rays of incident light have been proposed to overcome electro-optical challenges [2][3][4]. The BI process has been reported as one of the most promising technologies to improve optical performance [5,9].…”

mentioning

confidence: 99%

“…The FD capacitance causes a trade-off between conversion gain and full well capacity [4,6]. The imager uses a 1.65×1.65µm 2 4-shared-pixel FD boost-driving architecture with a view to optimize for high fill factor, high conversion gain and high full well capacity.…”

mentioning

confidence: 99%

“…A conventional FD driving image sensor achieves the FD potential not only using the coupling between the amplifier transistor's gate and the vertical signal line, but also using the coupling between the amplifier transistor's gate and drain line. These sensors are limited to a horizontal scanning time because the DRN electrodes have to be connected among all pixels or alternating from the left and right columns [4,7,8]. In this sensor, the DRN is separated from the amplifier drain electrode (VDD) because of the freedom in placing the metal wiring layer when using the BI process.…”

mentioning

confidence: 99%

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A 1/2.3-inch 10.3Mpixel 50frame/s Back-Illuminated CMOS image sensor

Wakabayashi¹,

Yamaguchi²,

Okano³

et al. 2010

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

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This paper presents a 1/2.3-inch 10.3Mpixel Back-Illuminated (BI) CMOS image sensor that targets both digital still camera (DSC) and high-definition camcorder applications. These applications require high-pixel-count, high-sensitivity, high saturation signal, low noise and high-speed imaging for image quality [1]. The sensor is scaled down to get a higher resolution due to higher pixel count. Several approaches such as a Cu process to reduce the pixel height and inner micro-lenses to gather rays of incident light have been proposed to overcome electro-optical challenges [2][3][4]. The BI process has been reported as one of the most promising technologies to improve optical performance [5,9]. This BI image sensor includes a 10b/12b analog-to-digital converter (ADC), an internal phase-locked loop (PLL) and a 10b serial LVDS interface to enable a data-rate up to 576MHz.Pixel sharing increases the sense-node capacitances because of: floating-diffusion (FD) regions linked in series, and interconnect capacitance. The FD capacitance causes a trade-off between conversion gain and full well capacity [4,6]. The imager uses a 1.65×1.65µm 2 4-shared-pixel FD boost-driving architecture with a view to optimize for high fill factor, high conversion gain and high full well capacity.

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A 1/2.7 inch Low-Noise CMOS Image Sensor for Full HD Camcorders

Cited by 33 publications

References 3 publications

[Paper] Floating Capacitor Load Readout Operation for Small, Low Power Consumption and High S/N Ratio CMOS Image Sensors

[Paper] Floating Capacitor Load Readout Operation for Small, Low Power Consumption and High S/N Ratio CMOS Image Sensors

A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple sampling

A 1/2.3-inch 10.3Mpixel 50frame/s Back-Illuminated CMOS image sensor

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