A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias

Miyazaki, Makoto; Ono, Go; Hattori, Toshihiro; Shiozawa, Kenji; Uchiyama, Kunio; Ishibashi, Koji

doi:10.1109/4.982427

Cited by 91 publications

(32 citation statements)

References 8 publications

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“…(8), the second term, which depends on both supply voltage and threshold voltage, has much less temperature dependence on the delay variation at the higher voltage region compared to the first term in Eq. (8). It is thus concluded that the temperature dependence of carrier mobility is a key factor in the variation of delay at a higher voltage.…”

Section: Temperature Variationmentioning

confidence: 99%

“…However, at lower voltage, the temperature coefficient gradually decreases with decreasing supply voltage as a result of the second term in Eq. (8). At a supply voltage of 1.1 V, the temperature coefficient of the delay becomes zero.…”

Section: Temperature Variationmentioning

confidence: 99%

“…(8). Figure 4 shows the simulated temperature coefficient of the delay in an inverter chain circuit as a function of supply voltage.…”

Section: Temperature Variationmentioning

confidence: 99%

“…Several compensation techniques have been reported [4]- [8]. In [4] and [5], a reference clock was used to compensate for the variations, and in [6]- [8], a substrate biasing or supply voltage control, or both, were used. However, these techniques involve the use of several circuit blocks and thus result in a complex and large-scale circuit configuration.…”

Section: Introductionmentioning

confidence: 99%

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An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs

Tsugita

Ueno

Hirose³

et al. 2010

IEICE Trans. Electron.

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SUMMARYAn on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed. Because the degradation of circuit performance originates from the variation of the saturation current in transistors, we developed a compensation circuit consisting of a reference current that is independent of PVT variations. The circuit is operated so that the saturation current in digital circuits is equal to the reference current. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-μm standard CMOS parameters. Monte Carlo simulations showed that the proposed technique effectively improves circuit performance by 71%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.

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Section: Temperature Variationmentioning

confidence: 99%

Section: Temperature Variationmentioning

confidence: 99%

“…(8). Figure 4 shows the simulated temperature coefficient of the delay in an inverter chain circuit as a function of supply voltage.…”

Section: Temperature Variationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs

Tsugita

Ueno

Hirose³

et al. 2010

IEICE Trans. Electron.

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“…Hence, it is essential to use techniques to manage the leakage energy [21,26]. Adaptive body bias (ABB) has been shown to be an effective technique to reduce leakage power Combined Time and Information Redundancy for SEU-Tolerance in Energy-Efficient Real-Time Systems [28] by tuning the threshold voltage of the transistors, reverse body bias (V sb < 0) to reduce sub-threshold leakage in standby mode and forward body bias (V sb > 0) to improve performance in active mode. To implement ABB in practice; generator circuits supplying the body bias voltages are required [29].…”

Section: Introductionmentioning

confidence: 99%

Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems

Ejlali

Al-Hashimi

Schmitz

et al. 2006

IEEE Trans. VLSI Syst.

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Abstract-Recently the trade-off between energy consumption and fault-tolerance in real-time systems has been highlighted. These works have focused on dynamic voltage scaling (DVS) to reduce dynamic energy dissipation and on time redundancy to achieve transient-fault tolerance. While the time redundancy technique exploits the available slack time to increase the faulttolerance by performing recovery executions, DVS exploits slack time to save energy. Therefore we believe there is a resource conflict between the time-redundancy technique and DVS. The first aim of this paper is to propose the usage of information redundancy to solve this problem. We demonstrate through analytical and experimental studies that it is possible to achieve both higher transient fault-tolerance (tolerance to single event upsets (SEU)) and less energy using a combination of information and time redundancy when compared with using time redundancy alone. The second aim of this paper is to analyze the interplay of transient-fault tolerance (SEU-tolerance) and adaptive body biasing (ABB) used to reduce static leakage energy, which has not been addressed in previous studies. We show that the same technique (i.e. the combination of time and information redundancy) is applicable to ABB-enabled systems and provides more advantages than time redundancy alone.

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Design of Low Dropout (LDO) Regulators

Chen¹

2016

Power Management Techniques for Integrated Circuit Design

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Low dropout (LDO) regulators are widely used in portable electronic devices because they occupy small chip and printed circuit board (PCB) areas. The performance advantages of these regulators include low quiescent current and wide bandwidth (BW), which result in fast transit response. Unlike switching regulators (SWRs), LDO regulators convert voltage through a linear operation, and thus a well-regulated output voltage can be derived without the occurrence of output voltage ripples. However, LDO regulators suffer from an inherent disadvantage, namely poor power conversion efficiency (PCE) if the ratio of the output voltage to the input voltage is small, because a large voltage stress over the pass transistor causes significant power loss. When considering the small silicon area, compact PCB, and reduced discrete component costs, an LDO regulator is one candidate that can provide a conversion function for regulated and scaled-down voltages. LDO regulators are frequently utilized as post-regulators in series with SWRs to suppress voltage ripples from the switching operation of SWRs caused by their large open-loop gain. In general, the combination of an SWR in series with an LDO regulator can be viewed as a simple and efficient power management module if the ratio of the output voltage to the input voltage, as well as the open-loop gain, can remain large in the LDO regulator. An LDO regulator is regarded as a voltage buffer for decreasing voltage ripples at the cost of slightly reduced PCE.LDO regulators have structures that are defined according to their controlling methods and compensated skills. As illustrated in Figure 2.1, LDO regulators may either be analog-low dropout (A-LDO) regulators or digital-low dropout (D-LDO) regulators. The controller of the former is designed with analog circuits, whereas that of the latter is designed with digital circuits. A-LDO regulators have two major categories, namely dominant pole compensation, which involves a large compensation capacitor C out located at the output node, and a capacitorfree (C-free) structure, which involves a dominant pole generated by Miller compensation capacitance.Power Management Techniques for Integrated Circuit Design, First Edition. Ke-Horng Chen.

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A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias

Cited by 91 publications

References 8 publications

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs

Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems

Design of Low Dropout (LDO) Regulators

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