Design of Low Dropout (LDO) Regulators

Abstract

Low dropout (LDO) regulators are widely used in portable electronic devices because they occupy small chip and printed circuit board (PCB) areas. The performance advantages of these regulators include low quiescent current and wide bandwidth (BW), which result in fast transit response. Unlike switching regulators (SWRs), LDO regulators convert voltage through a linear operation, and thus a well-regulated output voltage can be derived without the occurrence of output voltage ripples. However, LDO regulators suffer from an inherent disadvantage, namely poor power conversion efficiency (PCE) if the ratio of the output voltage to the input voltage is small, because a large voltage stress over the pass transistor causes significant power loss. When considering the small silicon area, compact PCB, and reduced discrete component costs, an LDO regulator is one candidate that can provide a conversion function for regulated and scaled-down voltages. LDO regulators are frequently utilized as post-regulators in series with SWRs to suppress voltage ripples from the switching operation of SWRs caused by their large open-loop gain. In general, the combination of an SWR in series with an LDO regulator can be viewed as a simple and efficient power management module if the ratio of the output voltage to the input voltage, as well as the open-loop gain, can remain large in the LDO regulator. An LDO regulator is regarded as a voltage buffer for decreasing voltage ripples at the cost of slightly reduced PCE.LDO regulators have structures that are defined according to their controlling methods and compensated skills. As illustrated in Figure 2.1, LDO regulators may either be analog-low dropout (A-LDO) regulators or digital-low dropout (D-LDO) regulators. The controller of the former is designed with analog circuits, whereas that of the latter is designed with digital circuits. A-LDO regulators have two major categories, namely dominant pole compensation, which involves a large compensation capacitor C out located at the output node, and a capacitorfree (C-free) structure, which involves a dominant pole generated by Miller compensation capacitance.Power Management Techniques for Integrated Circuit Design, First Edition. Ke-Horng Chen.