A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking

Kim, Jung-Sik; Oh, Changhoon; Lee, Hocheol; Lee, Donghyuk; Hwang, Hee-Chul; Hwang, Sooman; Na, Byongwook; Moon, Jin Young; Kim, Jin-Guk; Park, Hanna; Ryu, Jang-Woo; Park, Kiwon; Kang, Shin-Ho; Kim, Soyoung; Kim, Ho-Young; Bang, Jong-Min; Cho, Hyunyoon; Jang, Minsoo; Han, Cheolmin; Lee, Jung-Bae; Kyung, Kye-Hyun; Choi, Joon-Ho; Jun, Young-Hyun

doi:10.1109/jssc.2011.2164731

Cited by 152 publications

(65 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The CPU die and WideIO2 DRAM dies are connected by through-silicon vias (TSVs) [5], which have much lower RC-delay than the conventional off-package DRAM channels. However, this is only a half solution as more DRAM dies do not translate to higher DRAM bandwidth due to TSVs shared by all DRAM dies.…”

Section: Introductionmentioning

confidence: 99%

Energy-efficient heterogeneous memory system for mobile platforms

Shin

Jang

Lee

2017

IEICE Electron. Express

View full text Add to dashboard Cite

The bandwidth demands from mobile application processors (APs) have been consistently growing to run multiple compute-and memory-intensive workloads concurrently. The Low-Power Double-Data Rate (LPDDR) DRAM family has been the de-facto standard for main memory, whose operating frequency has been scaled up to meet these demands. However, frequency scaling poses many design challenges due to limited power budget, timing, and power/signal integrity issues. JEDEC has recently released the WideIO2 DRAM standard to provide high bandwidth at a low frequency. However, WideIO2 DRAM cannot completely replace LPDDR devices because it cannot provide enough capacity and bandwidth by itself. Thus, this paper proposes a heterogeneous mobile memory system (HMMS) using both types of DRAM devices. HMMS employs an efficient page migration scheme to serve more requests from energy-efficient WideIO2 DRAM devices. HMMS uses a small on-chip page location table at each DRAM controller to track page remappings without requiring a master table in off-chip DRAM. To minimize bandwidth and energy wastes from excessive page migrations, HMMS selects strong hot pages for migration, adjusts the page migration threshold dynamically and employs a migration stop mechanism. Our evaluation using 10 multi-programmed workloads demonstrates that HMMS improves the performance and energy-delay product (EDP) by 13% and 21%, respectively, over the baseline heterogeneous memory system with no migrations.

show abstract

Section: Introductionmentioning

confidence: 99%

Energy-efficient heterogeneous memory system for mobile platforms

Shin

Jang

Lee

2017

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…The floorplan of the DRAM dies is generated by referring to the die photos from [8]. The core and L2 cache areas for 22 nm technology nodes are obtained from McPAT [9].…”

Section: Baseline Systemmentioning

confidence: 99%

3D die-stacked DRAM thermal management via task allocation and core pipeline control

Yoon

Shim

Moon

et al. 2018

IEICE Electron. Express

View full text Add to dashboard Cite

A major hurdle to adopt 3D stacked DRAM is a thermal problem particularly when the DRAM dies are stacked above the processor dies. Exacerbated thermal problems in DRAM cause another problem which increases refresh rates to ensure data integrity of DRAM cells. In this paper, we propose two efficient techniques to address the thermal problem in 3D die-stacked DRAM by suppressing adverse thermal impacts from the processor die. Our thermal-aware task mapping technique allocates tasks to cores by considering computation-intensiveness of the workloads to minimize thermal interactions. The workload-aware core pipeline control technique adjusts pipeline widths (fetch and issue widths) of processor cores considering the workload characteristics. By adopting our proposed techniques, system-wide energy consumption is reduced by 7.6% while improving performance by 0.4% on average, thanks to the reduced pipeline widths and refresh rates. In terms of temperature, our techniques reduce the number of DRAM banks which exceed 85 degree Celsius by 92.8%, on average.

show abstract

“…In [32]- [34], the authors have demonstrated that implementing memory bus between a L2 cache and an on-chip main memory as wide as a cache line that operates at core's clock frequency can provide the maximum bandwidth that the L2 cache can consume and contribute to a larger gain in the system performance. In [35] and [36], 3-D stacked DRAM and SRAM caches with a vertical wide I/O interconnect have been fabricated at 50-nm and 0.18-μm technology nodes, respectively. In [37], a 3-D memory stacked system with 64 ARM Cortex-M3 cores has been fabricated at a 130-nm technology node.…”

Section: Related Workmentioning

confidence: 99%

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

Kang

Benini

Micheli

2015

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and low yield). In this paper, we propose a new TSV sharing method for a circuit-switched 3-D mesh-of-tree (MoT) interconnect, which supports high-throughput and lowlatency communication between processing cores and 3-D stacked multibanked L2 scratchpad memory. The proposed method supports traffic balancing and TSV-failure tolerant routing. The proposed method advocates a modular design strategy to allow stacking multiple identical memory dies without the need for different masks for dies at different levels in the memory stack. We also investigate various parameters of 3-D memory stacking (e.g., fabrication technology, TSV bonding technique, number of memory tiers, and TSV sharing scheme) that affect interconnect latency, system performance, and fabrication cost. Compared to conventional MoT interconnect [6] that is straightforwardly adapted to 3-D integration, the proposed method yields up to ×2.11 and ×1.11 improvements in terms of cost efficiency (i.e., performance/cost) for microbump TSV bonding and direct Cu-Cu TSV bonding techniques, respectively. Index Terms-3-D integration, multicore, networks-on-chip (NoC), scratchpad memory (SPM).

show abstract

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking

Cited by 152 publications

References 7 publications

Energy-efficient heterogeneous memory system for mobile platforms

Energy-efficient heterogeneous memory system for mobile platforms

3D die-stacked DRAM thermal management via task allocation and core pipeline control

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

Contact Info

Product

Resources

About