A 1.2-V 140-nW 10-bit Sigma–Delta Modulator for Electroencephalogram Applications

López-Morillo, E.; Carvajal, R.G.; Muñoz, F.; Gmili, H. El; Lopez-Martin, A.J.; Ramírez-Angulo, J.; Rodriguez‐Villegas, Esther

doi:10.1109/tbcas.2008.2001868

Cited by 28 publications

(9 citation statements)

References 16 publications

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“…In addition, low-voltage and lowpower analog and mixed signal ICs are required. To achieve the goal of reducing the supply voltage, we have an excellent choice which is to use bulk-driven OTAs operating in weak inversion region [1,2]. The mentioned technique is not only used to overcome the issues of the reduction of input voltage range, but also can provide high g m =I ratio, leading to high energy efficiency.…”

Section: Introductionmentioning

confidence: 99%

A transconductance enhancement technique for bulk-driven OTAs working in weak inversion

Cheng

Zhang

Zhao

2016

IEICE Electron. Express

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A proposed transconductance enhancement technique for bulkdriven OTAs working in weak inversion is presented in this paper. The basic idea is to use a bulk-driven input differential pair employing the auxiliary amplifier and positive feedback technique to enhance transconductance, which improves the enhancement ratio of transconductance from (n + 1)/ (n − 1) to (n + 2)/(n − 1). The proposed amplifier based on the mentioned technique is simulated on UMC 180 nm process with the help of Spectre. The simulation results demonstrate that the transconductance of the bulk-driven OTAs working in weak inversion improves almost 50% with just a little increased power consumption compared to the conventional counterparts.

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Section: Introductionmentioning

confidence: 99%

A transconductance enhancement technique for bulk-driven OTAs working in weak inversion

Cheng

Zhang

Zhao

2016

IEICE Electron. Express

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“…However, if a higher resolution circuit is implemented, then the power, chip area and cost of the DSP circuits also increase. Delta Sigma technology can be an attractive solution for the aforementioned challenges and has been widely applied in biomedical circuits and systems [7][8][9][10][11][12] because of its unique properties. First, it is well known that a Delta Sigma analog-to-digital converter (ADC) has much less circuit complexity and lower power consumption than multi-bit ADCs.…”

Section: Introductionmentioning

confidence: 99%

“…Although Delta Sigma technology has been widely used in converting analog signals to digital signals [7,9,11], it has not been commonly applied in DSP, because of the lack of Delta Sigma-based DSP circuits. Currently, the modulated Delta Sigma bit-stream is demodulated into a multi-bit stream and then processed by conventional multi-bit DSP circuits, as shown in Figure 1b [14].…”

Section: Introductionmentioning

confidence: 99%

Hardware-Efficient Delta Sigma-Based Digital Signal Processing Circuits for the Internet-of-Things

Liu

Furth

Tang

2015

JLPEA

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This paper presents hardware-efficient Delta Sigma linear processing circuits for the next generation low-power VLSI devices in the Internet-of-things (IoT). We first propose the P-N (positive-negative) pair method to manipulate both the analog value and length of a first-order Delta Sigma bit sequence. We then present a binary counter method. Based on these methods, we develop Delta Sigma domain on-the-fly digital signal-processing circuits: the Delta Sigma sum adder, average adder and coefficient multiplier. The counter-based average adder can work with both first-order and higher-order Delta Sigma modulators and can also be used as a coefficient multiplier. The functionalities of the proposed circuits are verified by MATLAB simulation and FPGA implementation. We also compare the area and power between the proposed Delta Sigma adders and a conventional multi-bit adder by synthesizing both circuits in the IBM 0.18-µm technology. Synthesis results show that the proposed Delta Sigma processing circuits can extensively reduce circuit area and power. With 100 inputs, a Delta Sigma average adder saves 94% of the silicon area and 96% of the power compared to a multi-bit binary adder. The proposed circuits have the potential to be widely used in future IoT circuits.

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“…Block diagram of a general purpose biopotential signal acquisition system. sigma-delta modulator [5], the energy harvesting unit [6], the sensor interface [7] and the voltage [8]. They, in conjunction, exhibit high potential for bringing down the power consumption of emerging bioelectronics.…”

mentioning

confidence: 99%

“…As shown in Fig. 1, the LPF's driving capability can be evaluated by the input capacitance of the subsequent signal processor (typically headed by a data converter with [5]), which can be co-designed to achieve the required LPF performances.…”

mentioning

confidence: 99%

15-nW Biopotential LPFs in 0.35-<formula formulatype="inline"> <tex Notation="TeX">$\mu{\rm m}$</tex></formula> CMOS Using Subthreshold-Source-Follower Biquads With and Without Gain Compensation

Zhang

Vai

Mak

et al. 2013

IEEE Trans. Biomed. Circuits Syst.

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Most biopotential readout front-ends rely on the g m- C lowpass filter (LPF) for forefront signal conditioning. A small g m realizes a large time constant ( τ = C / g m) suitable for ultra-low-cutoff filtering, saving both power and area. Yet, the noise and linearity can be compromised, given that each g m cell can involve one or several noisy and nonlinear V- I conversions originated from the active devices. This paper proposes the subthreshold-source-follower (SSF) Biquad as a prospective alternative. It features: 1) a very small number of active devices reducing the noise and nonlinearity footsteps; 2) No explicit feedback in differential implementation, and 3) extension of filter order by cascading. This paper presents an in-depth treatment of SSF Biquad in the nW-power regime, analyzing its power and area tradeoffs with gain, linearity and noise. A gain-compensation (GC) scheme addressing the gain-loss problem of NMOS-based SSF Biquad due to the body effect is also proposed. Two 100-Hz 4th-order Butterworth LPFs using the SSF Biquads with and without GC were fabricated in 0.35- μm CMOS. Measurement results show that the non-GC (GC) LPF can achieve a DC gain of -3.7 dB (0 dB), an input-referred noise of 36 μV rms (29 μV rms ), a HD3@60 Hz of -55.2 dB ( - 60.7 dB) and a die size of 0.11 mm² (0.08 mm²). Both LPFs draw 15 nW at 3 V. The achieved figure-of-merits (FoMs) are favorably comparable with the state-of-the-art.

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A 1.2-V 140-nW 10-bit Sigma–Delta Modulator for Electroencephalogram Applications

Cited by 28 publications

References 16 publications

A transconductance enhancement technique for bulk-driven OTAs working in weak inversion

A transconductance enhancement technique for bulk-driven OTAs working in weak inversion

Hardware-Efficient Delta Sigma-Based Digital Signal Processing Circuits for the Internet-of-Things

15-nW Biopotential LPFs in 0.35-<formula formulatype="inline"> <tex Notation="TeX">$\mu{\rm m}$</tex></formula> CMOS Using Subthreshold-Source-Follower Biquads With and Without Gain Compensation

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