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A: This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5-800 Mrad. Small prototypes of 64 × 64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. The collaboration is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.

This paper presents a second-order Sigma-Delta modulator for electroencephalogram applications with 10 bits of resolution, 1.2 V of supply voltage, and only 140 nW of power consumption over a bandwidth of 25 Hz. Low-voltage operation has been achieved using quasi-floating-gate-based circuits. The use of a new class-AB operational amplifier in weak inversion allows very low power consumption. Experimental results show an energy efficiency of 1.6 pJ per quantization level, making it the most energy-efficient converter reported to date in the very low signal bandwidth range.

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A Sigma-Delta (Σ∆) modulator with 10 bits of resolution and only 55 nW power consumption for electroencephalogram (EEG) applications is presented. The overall modulator operates from 1.2V using Quasi-FloatingGates (QFG) based circuits. The system has been implemented in a standard 0.5-µm CMOS process. Post-layout simulations have been performed showing 70 dB of SNR with an oversampling ratio of 64.