A low-voltage low-power QFG-based Sigma-Delta modulator for electroencephalogram applications

López-Morillo, E.; Carvajal, R.G.; Galán, J.; Ramírez-Angulo, J.; Lopez-Martin, A.J.; Rodriguez‐Villegas, Esther

doi:10.1109/biocas.2006.4600322

Cited by 9 publications

(8 citation statements)

References 13 publications

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“…In each pixel, the current Iph is integrated onto the capacitor Cint that produces a voltage drop proportional to the integration time and to the illumination. In every macro-pixel, the maximal voltage drop ΔV, corresponding to the pixel which receives the highest illumination, is determined by means of a Winner Take All (WTA) [8], [9], [10]. As long as the output of the WTA remains below Vref = ΔV/3, the pixel continues to integrate.…”

Section: Architecture Of the Feedback Loop Circuitmentioning

confidence: 99%

High Dynamic Range image sensor with self adapting integration time in 3D technology

Guezzi-Messaoud

Dupret

Peizerat

et al. 2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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Section: Architecture Of the Feedback Loop Circuitmentioning

confidence: 99%

High Dynamic Range image sensor with self adapting integration time in 3D technology

Guezzi-Messaoud

Dupret

Peizerat

et al. 2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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“…Dans chaque macropixel, la chute de tension ΔV maximale, correspondant au pixel qui reçoit la plus forte intensité lumineuse, est déterminée à l'aide d'un circuit Winner Take All. Classiquement utilisé dans les circuits neuromorphiques, le WTA (Winner-Take-All) est un circuit permettant d'extraire la tension maximum parmi toutes celles présentes à ses entrées (Carvajal et al, 2000 ;Soleimani et al, 2009) et (Lopez et al, 2006. Pour refléter le codage exponentiel, le temps d'intégration varie exponentiellement.…”

Section: Architecture D'ajustement Du Temps D'expositionunclassified

Capteur d’images à grande dynamique et compression intégrée pour technologie 3D

Guezzi-Messaoud¹,

Dupret²,

Peizerat³

et al. 2013

Traitement du signal

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A travers l'exploitation de l'intégration 3D, nous proposons d'améliorer la dynamique des capteurs d'images actuels et dépasser 120 dB. La technique utilisée se base sur l'adaptation du temps d'intégration par groupe de pixels en rétroagissant sur l'ensemble des pixels via les interconnexions verticales. L'architecture des pixels classiques, 3T ou 4T, n'est pas modifiée ce qui permet de bénéficier des hautes performances des imageurs classiques tout en rajoutant la grande dynamique. L'augmentation du nombre de bits pour représenter l'image grande dynamique est absorbée par une compression à deux niveaux, employée afin de réduire le flux de données en sortie du circuit tout en gardant la grande dynamique du signal. ABSTRACT. This paper presents a new High Dynamic Range (HDR) Image Sensor architecture that uses the capabilities of Three-Dimensional Integrated Circuit (3D IC) to attain a range of 120 dB without modifying the classic pixel architecture (3T, 4T). The integration time is evaluated by group of pixels on a stack IC and feedback by vertical interconnections to the sensor. A two level compression is then applied on the pixel groups to reduce the output data rate while keeping the high dynamic range.

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“…The combination of C 1 and M 10 can provide higher settling speed for the opamp while consuming less quiescent current [5]. Two transistors M 3 and M 4 are employed here to improve the phase margin of the opamp by pushing the right half plane zero, which is induced by the Miller capacitor C 2 , to high frequency while avoiding the usage of compensation resistor [6].…”

Section: A Front-end Amplifiermentioning

confidence: 99%

A 1-V 1.1-μW sensor interface IC for wearable biomedical devices

Zou

Tan

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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An ultra-low-power, low-noise sensor interface IC dedicated for bio-signal acquisition is presented in this paper. The proposed system architecture is optimized to achieve a better trade-off between power consumption and noise figure. A 0.05 ~ 200 Hz bandpass function is embedded within the frontend amplifier, and a wide bandwidth buffer is inserted between the front-end amplifier and ADC to facilitate a power-efficient interface. The system also includes an 11-bit SAR ADC with nonlinearity of less than ±0.7 LSB. The measured input-referred noise is 2.1 µV integrated across the pass-band, achieving Noise Efficiency Factor of 2.9, and the power consumption for the overall system is 1.1 µW under 1 V supply.

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A low-voltage low-power QFG-based Sigma-Delta modulator for electroencephalogram applications

Cited by 9 publications

References 13 publications

High Dynamic Range image sensor with self adapting integration time in 3D technology

High Dynamic Range image sensor with self adapting integration time in 3D technology

Capteur d’images à grande dynamique et compression intégrée pour technologie 3D

A 1-V 1.1-μW sensor interface IC for wearable biomedical devices

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