A 1.2-V 43.2-μW three-stage amplifier with cascode miller-compensation and Q-reduction for driving large capacitive load

Cheng, Qi; Hong, Zhiliang; Xue, Lizhong; Guo, Jianping

doi:10.1109/iscas.2016.7527276

Cited by 3 publications

(2 citation statements)

References 10 publications

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“…The relationship between Q-factor and gain peak in the Bode plot has been studied in [15]. In many three-stage amplifier designs [1][2][3][4][5][6][7][8][9][10], for their non-dominant complex-pole, the relevant Q-factor is normally set to be 1/ √ 2 to make the amplifiers feature with third-order Butterworth frequency response when they are configured as a unity-feedback system. However, the Q-factor is always changed according to different C L and thus 1/ √ 2 is the least value for Q max .…”

Section: Stability Analysis Under Large C L Variationmentioning

confidence: 99%

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Design and Analysis of Three-Stage Amplifier for Driving pF-to-nF Capacitive Load Based on Local Q-Factor Control and Cascode Miller Compensation Techniques

Cheng

Tang

et al. 2019

Electronics

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This paper presents a new frequency compensation approach for three-stage amplifiers driving a pF-to-nF capacitive load. Thanks to the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively, and the physical size of the compensation capacitors is also reduced. A local Q-factor control (LQC) loop is introduced to alter the Q-factor adaptively when loading capacitance CL varies significantly. This LQC loop decides how much damping current should be injected into the corresponding parasitic node to control the Q-factor of the complex-pole pair, which affects the frequency peak at the gain plot and the settling time of the proposed amplifier in the closed-loop step response. Additionally, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Simulated in 0.13-µm CMOS technology, the amplifier is verified to handle a 4-pF-to-1.5-nF (375× drivability) capacitive load with at least 0.88-MHz gain-bandwidth (GBW) product and 42.3° phase margin (PM), while consuming 24.0-µW quiescent power at 1.0-V nominal supply voltage.

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Section: Stability Analysis Under Large C L Variationmentioning

confidence: 99%

“…Generally speaking, there are at least three poles that exist in the transfer function of the loop gain of a three-stage amplifier. If the poles and zeros were distributed inappropriately, the multistage amplifier would encounter a closed-loop stability issue [5].…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Three-Stage Amplifier for Driving pF-to-nF Capacitive Load Based on Local Q-Factor Control and Cascode Miller Compensation Techniques

Cheng

Tang

et al. 2019

Electronics

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A cascode miller compensated three-stage amplifier with local Q-factor control for wide capacitive load applications

Cheng

Tang

et al. 2017

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

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3.6 mW Active-Electrode ECG/ETI Sensor System Using Wideband Low-Noise Instrumentation Amplifier and High Impedance Balanced Current Driver

Nguyen

Ali

Lee

2023

Sensors

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An active electrode (AE) and back-end (BE) integrated system for enhanced electrocardiogram (ECG)/electrode-tissue impedance (ETI) measurement is proposed. The AE consists of a balanced current driver and a preamplifier. To increase the output impedance, the current driver uses a matched current source and sink, which operates under negative feedback. To increase the linear input range, a new source degeneration method is proposed. The preamplifier is realized using a capacitively-coupled instrumentation amplifier (CCIA) with a ripple-reduction loop (RRL). Compared to the traditional Miller compensation, active frequency feedback compensation (AFFC) achieves bandwidth extension using the reduced size of the compensation capacitor. The BE performs three types of signal sensing: ECG, band power (BP), and impedance (IMP) data. The BP channel is used to detect the Q-, R-, and S-wave (QRS) complex in the ECG signal. The IMP channel measures the resistance and reactance of the electrode-tissue. The integrated circuits for the ECG/ETI system are realized in the 180 nm CMOS process and occupy a 1.26 mm2 area. The measured results show that the current driver supplies a relatively high current (>600 μApp) and achieves a high output impedance (1 MΩ at 500 kHz). The ETI system can detect resistance and capacitance in the ranges of 10 mΩ–3 kΩ and 100 nF–100 μF, respectively. The ECG/ETI system consumes 3.6 mW using a single 1.8 V supply.

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A 1.2-V 43.2-μW three-stage amplifier with cascode miller-compensation and Q-reduction for driving large capacitive load

Cited by 3 publications

References 10 publications

Design and Analysis of Three-Stage Amplifier for Driving pF-to-nF Capacitive Load Based on Local Q-Factor Control and Cascode Miller Compensation Techniques

Design and Analysis of Three-Stage Amplifier for Driving pF-to-nF Capacitive Load Based on Local Q-Factor Control and Cascode Miller Compensation Techniques

A cascode miller compensated three-stage amplifier with local Q-factor control for wide capacitive load applications

3.6 mW Active-Electrode ECG/ETI Sensor System Using Wideband Low-Noise Instrumentation Amplifier and High Impedance Balanced Current Driver

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