A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL

Urano, Yuki; Wang, Yun; Kuroda, Tadahiro; Ishikuro, Hiroki

doi:10.1109/iscas.2013.6572161

Cited by 9 publications

(2 citation statements)

References 7 publications

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“…The ever-increasing demand of transmitted data bandwidth requires high-throughput serial transceiver in integrated circuits (ICs) [1].In serial links, the clock and data recovery circuit (CDR) in the receiver is a core block, which is generally used to extract the clock information from serial data stream and retime data signal to the optimal retiming position. To meet the requirements of both high and low speed operations, a wide-range CDR is needed.…”

Section: Introductionmentioning

confidence: 99%

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180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance

Liu

Wang

Jia

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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A wide range delay-locked loop (DLL) based clock and data recovery (CDR) circuit including coarse and fine tune blocks is proposed in this paper. The coarse tune block adopts a time to digital converter and digital control delay line to widen the frequency capture range, reduce locking time and prevent the false locking problem. In the fine tune block, a novel phase detector combines the tasks of sampling and charge-pump using half rate clock. Starting-control circuit can ensure CDR takes full use of the delay range provided by voltage control delay line. Moreover, a fully analog DLL technique is applied to exploit the benefits of low skew and jitter performance. The simulation result shows the proposed CDR can cover a wide frequency range from 180.5Mbps to 8Gbps, while the peak-to-peak jitter of recovery clock is 2.7ps at 200Mbps and 1.06ps at 8Gbps. Fabricated in a 65nm CMOS process, this design dissipates 9.9mW and 22.9mW respectively at 200 Mbps and 8Gbps from a 1.2 V supply. Keywords-Clock and data recovery (CDR), wide-range, delaylocked loop (DLL), low jitter, time-to-digital converter (TDC)

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Section: Introductionmentioning

confidence: 99%

“…As the number of VCDL increases, the mismatches between the VCDLs, increased area and power consumption will become more and more serious. Oversampled phase picking technology [1] also has been adopted, however, the phase jumps between adjacent sampling clocks lead to unavoidable jitter.…”

Section: Introductionmentioning

confidence: 99%

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance

Liu

Wang

Jia

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Pulsed Decimal Encoding for IoT Single-Channel Dynamic Signaling

Muzaffar

Elfadel

2019

VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things

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Pulsed-Index Communication (PIC) is a recent technique for single-channel communication that is based on the principle of transmitting the indices of only the ON bits as a series of pulse streams. In this paper, a modified version of PIC, called Pulsed Decimal Communication (PDC), is presented that uses the same underlying principle but with key improvements in data rate and reliability. Like PIC, PDC is a protocol for single-channel, high-data rate, low-power dynamic signaling that does not require any clock and data recovery. It consists of a three-step algorithm, comprising a segmentation, an encoding, and a sub-segmentation step to achieve higher data rates. The segmentation step splits the data word into smaller segments and therefore smaller decimal numbers to represent them. The encoding step reduces the number of ON bits in the data and relocates them to lower indices. The sub-segmentation step further splits the segments into smaller sub-segments. The complete process significantly reduces the total number of pulses required for transmitting binary data, thus improving the data rate by about 78% . A theoretical model of the PDC protocol is exploited to estimate its data rate and derive the optimum segmentation. Furthermore, PDC is shown to be more reliable than PIC as it eliminates the variations in the number of symbols to be transmitted. The FPGA and ASIC (65nm technology) implementations of PDC show that the low-power operation and small footprint of PIC are preserved. PDC consumes around 25µW of power at a clock frequency of 25M Hz with a gate count of approximately 2150 gates.

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Edge-Coded Signaling Techniques

Muzaffar

Elfadel²

2022

Secure, Low-Power IoT Communication Using Edge-Coded Signaling

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A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL

Cited by 9 publications

References 7 publications

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance

Pulsed Decimal Encoding for IoT Single-Channel Dynamic Signaling

Edge-Coded Signaling Techniques

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